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Preliminary Data Sheet February 1999
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Features
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Applications
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Thirty-two full-duplex, serial time-division multiplexed (TDM) highways. Full availability, nonblocking 2048-channel time/ space switch. 2.048 Mbits/s (32 time slots), 4.096 Mbits/s (64 time slots), or 8.192 Mbits/s (128 time slots) data rates, independently programmable per highway. 64 kbits/s granularity with optional 32 kbits/s (4-bit) and 16 kbits/s (2-bit) subrate switching, selectable per highway. Low-latency mode for voice channels. Frame integrity for wideband data applications. Concentration highway interface (CHI) compatible with the IOM2, GCI, K2, SLD, MVIP*, ST-Bus, SC-Bus, and H.100. Single highway clock and frame synchronization input. Independently programmable bit and byte offsets with 1/4 bit resolution for all highways. Capable of broadcasting data to the transmit highways from a variety of sources including host data. High-impedance control per time slot. Software-compatible family of 1K, 2K, and 4K timeslot interchangers. Thirty-two independent high-impedance indicators (output enables) for transmit highways, allowing external drivers. Direct access to device registers, connection store, and data store via microprocessor interface. IEEE 1149.1 boundary scan (JTAG). Test-pattern generation and checking for on-line system testing (PRBS, QRSS, or user-defined byte). User-accessible BIST for data and connection stores. 3.3 V power supply with 5 V tolerant I/O. Low-power, high-density CMOS technology, and TTL compatible switching thresholds. 217-pin PBGA package. -40 C to +85 C operating temperature range.
Small and medium digital switch matrices. Computer telephony integration (CTI). Access concentrators. PABX. Cellular infrastructure. ISP modem banks. T1/E1 multiplexers. Digital cross connects. Digital loop carriers. Multiport DS1/E1 service cards. LAN/WAN gateways. TDM highway data rate adaptation.
Description
The TTSI2K32T Time-Slot Interchanger (TSI) switches data between 32 full-duplex, serial, timedivision multiplexed highways. The TTSI2K32T can make any connection between 2048 input and output time slots. Each of the 32 transmit and 32 receive highways can be independently programmed for data rate (2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s) and offset. The offset can range from 0 bits to 127 bytes and 7 3/4 bits on a 8.192 Mbits/s highway. The TTSI2K32T can perform rate adaptation between varying speed highways as well. The TTSI2K32T is configured via a microprocessor interface with a demultiplexed address and data bus. In addition to accessing the registers and connection store, this interface can also be used to read received time slots and specify user data for transmission. The TTSI2K32T ensures that interchanged time slots retain their frame integrity. Frame integrity is required for applications that switch wideband data (i.e., ISDN H-channels). For voice applications where low delay is important, a low-latency mode can be selected.
* MVIP is a registered trademark of Natural Microsystems Corporation. IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet February 1999
Table of Contents
Contents Page
Features .................................................................................................................................................................. 1 Applications ............................................................................................................................................................. 1 Description............................................................................................................................................................... 1 Functional Description ............................................................................................................................................. 5 Pin Information ........................................................................................................................................................ 7 Typical TSI Application .......................................................................................................................................... 15 Interchange Fabric................................................................................................................................................. 16 Small and Large TSIs ............................................................................................................................................ 17 Microprocessor Interface ....................................................................................................................................... 18 Asynchronous Mode (MM = 0)........................................................................................................................... 18 Synchronous Mode (MM = 1) ............................................................................................................................ 19 Highway Data Rate Selection................................................................................................................................ 20 Mixed-Highway Data Rates ................................................................................................................................... 21 TDM Highway Interface Timing ............................................................................................................................. 22 Virtual and Physical Frames .............................................................................................................................. 22 TDM Highway Alignment at Zero Offset ............................................................................................................ 23 TDM Highway Offsets............................................................................................................................................ 23 Reset Sequence .................................................................................................................................................... 24 Low-Latency and Frame-Integrity Modes .............................................................................................................. 25 Low Latency....................................................................................................................................................... 25 Frame Integrity................................................................................................................................................... 26 Test-Pattern Generation ........................................................................................................................................ 29 Test-Pattern Checking........................................................................................................................................... 29 Error Injection ........................................................................................................................................................ 30 Error Checking....................................................................................................................................................... 30 JTAG Boundary-Scan Specification ...................................................................................................................... 31 Principle of the Boundary Scan.......................................................................................................................... 31 Test Access Port Controller ............................................................................................................................... 32 Instruction Register ............................................................................................................................................ 34 Boundary-Scan Register.................................................................................................................................... 35 BYPASS Register .............................................................................................................................................. 35 IDCODE Register............................................................................................................................................... 35 3-State Procedures ............................................................................................................................................ 35 Register Architecture ............................................................................................................................................. 36 Configuration Register Architecture....................................................................................................................... 38 Transmit Highway 3-State Options .................................................................................................................... 51 Data Store Memory ............................................................................................................................................... 52 Connection Store Memory..................................................................................................................................... 52 Absolute Maximum Ratings................................................................................................................................... 55 Operating Conditions............................................................................................................................................. 55 Handling Precautions ............................................................................................................................................ 55 Electrical Characteristics ....................................................................................................................................... 56 Timing Characteristics ........................................................................................................................................... 56 Outline Diagram..................................................................................................................................................... 63 217-Pin PBGA.................................................................................................................................................... 63 Ordering Information.............................................................................................................................................. 64 DS99-045T1E1 Replaces DS97-475TIC to Incorporate the Following Updates ................................................... 64
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Lucent Technologies Inc.
Preliminary Data Sheet February 1999
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
List of Figures
Figures Page
Figure 1. Block Diagram of the TTSI2K32T .............................................................................................................6 Figure 2. 217-Pin PBGA (Bottom View) ...................................................................................................................7 Figure 3. A Typical TSI Application ........................................................................................................................15 Figure 4. An 8K Time-Slot Switch Made from 4K TSIs ..........................................................................................17 Figure 5. Asynchronous Read................................................................................................................................18 Figure 6. Asynchronous Write................................................................................................................................18 Figure 7. Synchronous Read .................................................................................................................................19 Figure 8. Synchronous Write..................................................................................................................................19 Figure 9. Mixed-Highway Data Rates ....................................................................................................................21 Figure 10. Virtual and Physical Frames .................................................................................................................22 Figure 11. Synchronization to FSYNC ...................................................................................................................23 Figure 12. Highway Offsets ....................................................................................................................................24 Figure 13. Mixed Low-Latency and Frame-Integrity Modes ...................................................................................28 Figure 14. Block Diagram of the TTSI2K32T's Boundary-Scan Test Logic ...........................................................31 Figure 15. BS TAP Controller State Diagram.........................................................................................................32 Figure 16. Asynchronous Read Cycle Timing Using DT Handshake.....................................................................57 Figure 17. Asynchronous Write Cycle Timing Using DT Handshake .....................................................................57 Figure 18. Asynchronous Read Cycle Timing Using Only CS ...............................................................................58 Figure 19. Asynchronous Write Cycle Timing Using Only CS ...............................................................................58 Figure 20. Synchronous Read Cycle Timing..........................................................................................................59 Figure 21. Synchronous Write Cycle Timing ..........................................................................................................59 Figure 22. TDM Highway Timing............................................................................................................................61 Figure 23. JTAG Interface Timing ..........................................................................................................................62
Lucent Technologies Inc.
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TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet February 1999
List of Tables
Tables Page
Table 1. Data Rate and Switch Size Examples ....................................................................................................... 5 Table 2. Pin Assignments for a 217-Pin PBGA--Pin Number Order ...................................................................... 8 Table 3. Pin Assignments for a 217-Pin PBGA--Signal Name Order................................................................... 10 Table 4. TTSI2K32T Pin Descriptions ................................................................................................................... 12 Table 5. The TSI Family ........................................................................................................................................ 17 Table 6. Rx Highway Data Rate Options............................................................................................................... 20 Table 7. Tx Highway Data Rate Options ............................................................................................................... 20 Table 8. Time-Slot Separation Required for Transmission with Minimum Latency (0 Offsets) ............................. 25 Table 9. Offset Difference and Its Effect on Frame for Transmission.................................................................... 27 Table 10. Offset Difference Boundaries ................................................................................................................ 27 Table 11. TAP Controller States in the Data Register Branch............................................................................... 33 Table 12. TAP Controller States in the Instruction Register Branch...................................................................... 33 Table 13. TTSI2K32T's Boundary-Scan Instructions ............................................................................................ 34 Table 14. TTSI2K32T Register Summary ............................................................................................................. 36 Table 15. General Command Register (0x00) ...................................................................................................... 38 Table 16. Software Reset Register (0x01) ............................................................................................................ 39 Table 17. BIST Command Register (0x02) ........................................................................................................... 39 Table 18. Idle Code 1 Register (0x03)................................................................................................................... 40 Table 19. Idle Code 2 Register (0x04)................................................................................................................... 40 Table 20. Idle Code 3 Register (0x05)................................................................................................................... 40 Table 21. Global Interrupt Mask Register (0x06)................................................................................................... 40 Table 22. Interrupt Status Register (0x07) ............................................................................................................ 41 Table 23. Interrupt Mask Register (0x08) .............................................................................................................. 42 Table 24. Test Command Register (0x09) ............................................................................................................ 43 Table 25. Test-Pattern Style Register (0x0A)........................................................................................................ 44 Table 26. Test-Pattern Checker Highway Register (0x0B).................................................................................... 45 Table 27. Test-Pattern Checker Upper Time-Slot Register (0x0C) ....................................................................... 45 Table 28. Test-Pattern Checker Lower Time-Slot Register (0x0D) ....................................................................... 45 Table 29. Test-Pattern Checker Data Register (0x0E).......................................................................................... 45 Table 30. Test-Pattern Error Injection Register (0x0F).......................................................................................... 45 Table 31. Test-Pattern Error Counter (Byte 0) (0x10) ........................................................................................... 46 Table 32. Test-Pattern Error Counter (Byte 1) (0x11) ........................................................................................... 46 Table 33. Test-Pattern Generator Data Register (0x12) ....................................................................................... 46 Table 34. Version Register (0x13)......................................................................................................................... 46 Table 35. Transmit Highway Configuration Register (Byte 0) (0x1000 + 4i) ......................................................... 47 Table 36. Transmit Highway Configuration Register (Byte 1) (0x1001 + 4i) ......................................................... 48 Table 37. Transmit Highway Configuration Register (Byte 2) (0x1002 + 4i) ......................................................... 48 Table 38. Receive Highway Configuration Register (Byte 0) (0x1800 + 4i) .......................................................... 49 Table 39. Receive Highway Configuration Register (Byte 1) (0x1801 + 4i) .......................................................... 50 Table 40. Receive Highway Configuration Register (Byte 2) (0x1802 + 4i) .......................................................... 50 Table 41. Transmit Highway 3-State Options........................................................................................................ 51 Table 42. Address Scheme for Data Store Memory ............................................................................................. 52 Table 43. Address Scheme for Connection Store Memory .................................................................................. 52 Table 44. Connection Store Memory (Byte 0) ....................................................................................................... 53 Table 45. Connection Store Memory (Byte 1) ....................................................................................................... 53 Table 46. Clock Specifications .............................................................................................................................. 56 Table 47. Asynchronous Read and Write Interface Timing Using DT Handshake................................................ 57 Table 48. Asynchronous Microprocessor Interface Timing Using Only CS .......................................................... 58 Table 49. Synchronous Microprocessor Interface Timing ..................................................................................... 60 Table 50. TDM Highway Timing ............................................................................................................................ 61 Table 51. JTAG Interface Timing........................................................................................................................... 62
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Lucent Technologies Inc.
Preliminary Data Sheet February 1999
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Functional Description
The TTSI2K32T is a 2048 time-slot switch that can be used in a variety of ways, with some or all of the highways active and running at different data rates. The table below lists a few of the possible combinations of switch size and data rates. By selecting different rates for receive and transmit highways, rate adaptation can be performed also. Each one of the 64 (32 transmit and 32 receive) highways can be independently programmed for data rate (2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s) as well as a full range of bit (0--7.75) and byte (0--127) offsets. Table 1. Data Rate and Switch Size Examples Number of Receive Highways Used 32 16 16 16 and 8 Receive Highway Data Rates (Mbits/s) 4.096 8.192 8.192 4.096 8.192 Receive Time Slots per Frame 64 128 128 64 128 Total Switch Size 2048 2048 2048 2048 Number of Transmit Highways Used 32 16 32 10 and 11 Transmit Highway Data Rates (Mbits/s) 4.096 8.192 4.096 4.096 8.192 Transmit Time Slots per Frame 64 128 64 64 128
This device uses a single clock (CK) and frame synchronization (FSYNC) signal for all highways. The CK rate can be 2.048 MHz, 4.096 MHz, 8.192 MHz, or 16.384 MHz, and this speed is indicated to the device via the CKSPD [0--2] strap pins. A pulse is expected on the FSYNC pin once every 125 s. Each one of the 2048 time slots can be independently programmed in any one of the data modes listed below:
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Low latency Frame integrity Host data substitution Idle code substitution Test-pattern substitution (PRBS, QRSS, or a fixed byte) High impedance
The low-latency mode causes a receive highway time slot to be transmitted as soon as possible, which is dependent on the relative offset of the input and output time slots. This mode is useful for voice channels where it is important to keep the transmission delay to a minimum. The frame integrity mode will guarantee that all selected time slots received in a common frame will be transmitted together in a common frame. This mode is useful for wideband data (e.g., ISDN H-channels) where multiple time slots received in a single frame cannot be split across two transmit frames. The TTSI2K32T is a nonblocking DS0 (64 kbits/s channel) switch where a time slot is 8 bits. Since each Rx and Tx highway data rate can be individually selected, the TTSI2K32T can also be used to switch time slots that are smaller than 8 bits.
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32 kbits/s channels (4-bit time slots) such as in compressed voice (ADPCM) applications. The TTSI2K32T will be configured to sample the data at twice the data rate for highways carrying traffic at 2.048 Mbits/s or 4.096 Mbits/s. 16 kbits/s channels (2-bit time slots) such as in cellular (GSM) applications. The TTSI2K32T will be set to sample the data at four times the data rate on a 2.048 Mbits/s highway carrying such traffic. 8 kbits/s channels (1-bit time slots) such as in half-rate GSM applications. This can be done by looping the data through the TSI multiple times, thus oversampling the same data multiple times. However, in this configuration, the total switching capacity of the device will drop and the latency will go up.
The TTSI2K32T is one in a family of 1K, 2K, and 4K TSIs. The high-impedance control per time-slot feature allows four of the 4K devices to be connected to make an 8K time-slot switch. If external drivers are needed on the transmit highway pins, support for 32 output enables, corresponding to the 32 transmit highways, is provided. Lucent Technologies Inc. 5
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet February 1999
Functional Description (continued)
The device capabilities include several test features for board and device diagnostics.
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Test-pattern checking on input time slots (PRBS, QRSS, or a fixed byte). Test-pattern generation on output time slots (PRBS, QRSS, or a fixed byte). JTAG on all I/O. Software-controlled BIST of data store and connection store memory. TEST pin for isolating the TTSI2K32T during board test.
The microprocessor interface supports two modes of operation, synchronous and asynchronous. These modes are selected based on the MM input pin. Both modes provide an 8-bit demultiplexed address and data bus. Fifteen address pins allow direct access to the 32 Kbyte address space. This interface provides direct access to the control registers and data store and connection store memories. The TTSI2K32T is fabricated using a low-power, high-density, CMOS process that nominally operates at 3.3 V with TTL switching thresholds and 5 V tolerance on the inputs and outputs. A basic block diagram of the architecture is shown in Figure 1.
RXD0 RXD1 RXD2 RXD3 RECEIVE HIGHWAYS TDM DATA TDM DATA
TXD0 TXOE0 TXD1 TRANSMIT HIGHWAYS TXOE1
DATA STORE
RXD30 RXD31
TXD31 TXOE31
FSYNC DATA STORE ADDRESS CK CKSPD0 CKSPD1 CKSPD2 PLL AND CK LOGIC CONNECTION STORE JTAG TCK TDI TMS TRST TDO
HOST ADDRESS/DATA BUS
RESET TEST
MM
MICROPROCESSOR INTERFACE
INT
A[14--0]
D[7--0]
CS
AS
DS
R/W
PCLK
DT
5-5780(F).br.1
Figure 1. Block Diagram of the TTSI2K32T 6 Lucent Technologies Inc.
Preliminary Data Sheet February 1999
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Pin Information
The TTSI2K32T is available in a 217-pin PBGA with 1.27 mm (50 mil) pin pitch.
U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
5-6953(F)
SIGNAL/PWR/GND THERMAL BALLS (SHOULD BE CONNECTED TO CIRCUIT BOARD'S GROUND PLAN) Figure 2. 217-Pin PBGA (Bottom View)
Lucent Technologies Inc.
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TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet February 1999
Pin Information (continued)
Table 2. Pin Assignments for a 217-Pin PBGA--Pin Number Order Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C1 C2 C3 C4 8 Signal Name NC NC NC TXOE1 TXD18 TXD2 VDD NC VDDPLL CKSPD0 CKSPD2 TXD3 NC TXOE22 TXD21 NC VSS RXD25 VSS TXOE0 NC TXD1 TXOE2 NC VSSPLL CK CKSPD1 VDD NC TXD4 TXOE21 NC VSS RESET VDD RXD24 VSS TXD0 Pin C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 E1 E2 E3 E4 E14 E15 E16 E17 Signal Name TXD15 TXOE18 TXOE19 TXD19 NC TXOE3 TXD20 TXOE4 TXD22 TXD23 VSS TEST TCK RXD6 RXD7 RXD23 VSS TXOE15 VDD NC VDD VSS VDD TXOE20 VDD TXOE23 VSS TDI TMS TRST RXD12 RXD21 RXD13 RXD14 TDO VDD TXOE16 TXOE17 Pin F1 F2 F3 F4 F14 F15 F16 F17 G1 G2 G3 G4 G14 G15 G16 G17 H1 H2 H3 H4 H8 H9 H10 H14 H15 H16 H17 J1 J2 J3 J4 J8 J9 J10 J14 J15 J16 J17 Signal Name RXD4 VDD RXD20 RXD22 NC TXD16 NC TXD17 RXD3 VDD RXD5 RXD19 TXD26 TXOE26 TXOE24 TXD24 VDD RXD2 NC VDD VSS VSS VSS VDD FSYNC VDD TXOE5 RXD0 RXD1 A7 VSS VSS VSS VSS VSS TXD5 TXD8 TXOE8 Pin K1 K2 K3 K4 K8 K9 K10 K14 K15 K16 K17 L1 L2 L3 L4 L14 L15 L16 L17 M1 M2 M3 M4 M14 M15 M16 M17 N1 N2 N3 N4 N14 N15 N16 N17 P1 P2 P3 Signal Name RXD11 RXD10 RXD18 VDD VSS VSS VSS VDD NC TXD9 TXOE9 RXD17 VDD RXD16 RXD9 TXOE6 VDD NC TXOE10 RXD8 A8 A10 VDD TXOE25 VSS VSS TXD10 A9 A11 A13 NC TXOE11 INT TXOE7 TXD6 A12 A14 RXD26
Lucent Technologies Inc.
Preliminary Data Sheet February 1999
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Pin Information (continued)
Table 2. Pin Assignments for a 217-Pin PBGA--Pin Number Order (continued) Pin P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 T1 T2 T3 T4 T5 T6 T7 Signal Name VSS VDD A2 TXD30 VDD VSS VDD TXOE29 D6 NC VSS CS TXD25 TXD7 MM RXD27 VSS RXD31 A3 NC TXOE31 TXD14 D0 D2 TXD28 VDD D7 TXD12 VSS AS VDD RXD28 VSS RXD30 A1 A5 TXD31 TXOE30 9 Pin T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 Signal Name DS DT VDD TXD29 TXD27 D4 TXD13 TXOE12 VSS NC RXD15 RXD29 A0 A4 A6 VDD TXOE14 PCLK NC D1 D3 TXOE28 TXOE27 D5 TXOE13 TXD11 R/W
Lucent Technologies Inc.
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet February 1999
Pin Information (continued)
Table 3. Pin Assignments for a 217-Pin PBGA--Signal Name Order Signal Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 AS CK CKSPD0 CKSPD1 CKSPD2 CS D0 D1 D2 D3 D4 D5 D6 D7 DS DT FSYNC INT MM NC NC NC NC 10 Pin U3 T4 P6 R5 U4 T5 U5 J3 M2 N1 M3 N2 P1 N3 P2 R16 B9 A10 B10 A11 P15 R9 U10 R10 U11 T13 U14 P12 R13 T8 T9 H15 N15 R1 A1 A2 A3 A13 Signal Name NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC PCLK R/W RESET RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 RXD8 RXD9 RXD10 RXD11 RXD12 RXD13 RXD14 RXD15 RXD16 Pin A16 B4 B7 B12 B15 D7 F14 F16 H3 K15 L16 N4 P13 R6 T17 U9 C9 A8 U8 U17 B17 J1 J2 H2 G1 F1 G3 D1 D2 M1 L4 K2 K1 E1 E3 E4 U1 L3 Signal Name RXD17 RXD18 RXD19 RXD20 RXD21 RXD22 RXD23 RXD24 RXD25 RXD26 RXD27 RXD28 RXD29 RXD30 RXD31 TCK TDI TDO TEST TMS TRST TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 TXD8 TXD9 TXD10 TXD11 TXD12 TXD13 TXD14 TXD15 TXD16 Pin L1 K3 G4 F3 E2 F4 D3 C2 B1 P3 R2 T1 U2 T3 R4 C17 D15 E14 C16 D16 D17 C4 B5 A6 A12 B13 J15 N17 P17 J16 K16 M17 U16 R14 T14 R8 C5 F15 Signal Name TXD17 TXD18 TXD19 TXD20 TXD21 TXD22 TXD23 TXD24 TXD25 TXD26 TXD27 TXD28 TXD29 TXD30 TXD31 TXOE0 TXOE1 TXOE2 TXOE3 TXOE4 TXOE5 TXOE6 TXOE7 TXOE8 TXOE9 TXOE10 TXOE11 TXOE12 TXOE13 TXOE14 TXOE15 TXOE16 TXOE17 TXOE18 TXOE19 TXOE20 TXOE21 TXOE22 Pin F17 A5 C8 C11 A15 C13 C14 G17 P16 G14 T12 R11 T11 P7 T6 B3 A4 B6 C10 C12 H17 L14 N16 J17 K17 L17 N14 T15 U15 U7 D5 E16 E17 C6 C7 D11 B14 A14
Lucent Technologies Inc.
Preliminary Data Sheet February 1999
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Pin Information (continued)
Table 3. Pin Assignments for a 217-Pin PBGA--Signal Name Order (continued) Signal Name TXOE23 TXOE24 TXOE25 TXOE26 TXOE27 TXOE28 TXOE29 TXOE30 TXOE31 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDPLL VSS VSS Pin D13 G16 M14 G15 U13 U12 P11 T7 R7 A7 B11 C1 D6 D8 D10 D12 E15 F2 H4 H14 H16 K4 K14 L2 L15 M4 P5 P8 P10 R12 R17 T10 U6 G2 H1 A9 B2 B16 11 Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSPLL Pin C3 C15 D4 D9 D14 H8 H9 H10 J4 J8 J9 J10 J14 K8 K9 K10 P4 P9 P14 R3 R15 T2 T16 M15 M16 A17 B8
Lucent Technologies Inc.
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet February 1999
Pin Information (continued)
Table 4. TTSI2K32T Pin Descriptions Symbol RESET Type* I Description Reset (Active-Low). A low on this pin resets the TTSI2K32T. It is asynchronous to any other clock or input signal. All flip-flops will be cleared when RESET is low. All counters, state machines, and configuration registers will be set to the default state following a reset. Test (Active-Low). When low, TEST causes the output and bidirectional pins of the TTSI2K32T device to be in a high-impedance state. This pin has an internal pull-up resistor. Microprocessor Mode. When MM = 0, the TTSI2K32T uses an asynchronous type handshake (equal to mode 1 of the Lucent dual T1/E1 terminator devices). When MM = 1, the TTSI2K32T uses a synchronous type handshake which requires a host processor clock (PCLK) input. Both modes use a demultiplexed address and data bus. Synchronous Mode (MM = 1) I I Host Processor Clock. Valid from 0 MHz to 65 MHz. Address Valid (Active-Low). Valid for one PCLK cycle. Indicates the start of a processor access. Chip Select (Active-Low). This pin is asserted low to enable any transfers through the microprocessor interface. CS should be a decode of all address and cycle type signals defining the memory map location of the TTSI2K32T. Asynchronous Mode (MM = 0) Unused. Must be either tied high or low. Address Valid (Active-Low). Indicates a valid address for a processor access. Must be held low for the duration of the access. Chip Select (Active-Low). This pin is asserted low to enable any transfers through the microprocessor interface. CS should be a decode of all address and cycle type signals defining the memory map location of the TTSI2K32T. In this mode, CS is used to control the tristating of DT at the end of the cycle. The input timing requirement of CS relative to AS is described in the Timing Characteristics section on page 56. Data Valid (Active-Low). Indicates valid data during processor writes. The TTSI2K32T will start driving D[7--0] when this signal is asserted during processor reads. Data Transfer Acknowledge (ActiveLow). Indicates that data has been written during processor writes. Indicates that read data is valid during processor reads. Once driven active, this signal is held active until AS , DS, or CS is removed. An external pull-up is required on this output.
* Iu indicates internal 100 k pull-up resistor, and Id indicates 17.5 k pull-down resistor.
TEST
Iu
MM
I
-- PCLK AS
CS
I
DS
I
Not Used. Must be tied high.
DT
O
Data Transfer Acknowledge (ActiveLow). Active for one PCLK cycle. Indicates that data has been written during processor writes. Indicates that read data is valid during processor reads. An external pull-up is required on this output.
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Lucent Technologies Inc.
Preliminary Data Sheet February 1999
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Pin Information (continued)
Table 4. TTSI2K32T Pin Descriptions (continued) Symbol D[7-- 0] Type* I/O Description Host Processor Data Bus. These pins provide an 8-bit, bidirectional data bus. Read data is valid for one PCLK cycle coincident with the assertion of DT. Write data must be held throughout the access. Host Processor Data Bus. These pins provide an 8-bit, bidirectional data bus. Write data must be valid for the duration of DS. Read data is valid while DT is asserted.
A[14-- 0]
I
Host Processor Address Bus. A14--A0 must remain valid throughout the entire processor access. A0 is the least significant address signal and is used to select byte locations. Read/Write. This signal indicates a read or write cycle. Read cycle is indicated with a logic 1; a write cycle is indicated with a logic 0. Interrupt. This pin will be asserted to indicate that an interrupt condition has occurred. This output will remain active until the interrupt status register has been cleared (read). The polarity of this output is controlled through the INTP bit (bit 3) of the general command register. The default value of this register is 0, which indicates active-high. This output is tristated until INTOE (bit 4) of the general command register is set to 1. The polarity of this output should be selected before the pin is enabled. Receive Data Highways 0--31. Serial TDM highways receiving data at rates of 2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s. Frame Synchronization. This signal indicates the beginning of a frame every 125 s (8 kHz). FSYNC can be active-low or active-high, but its polarity is the same for all highways. FSYNC can be sampled on a positive or negative CK edge. Timeslot numbers and bit offsets are assigned relative to the detection of FSYNC. There are no restrictions on the duty cycle of FSYNC as long as the setup and hold timing requirements relative to CK are met. Clock. This input is the clock reference for all the transmit and receive highways. Its frequency can be 2.048 MHz, 4.096 MHz, 8.192 MHz, or 16.384 MHz. The frequency selection for CK must be set equal to or greater than the fastest highway data rate. Clock Speed Select for CK Pin. These strap pins indicate the frequency of CK: CKSPD2 0 0 0 0 1 CKSPD1 0 0 1 1 X CKSPD0 0 1 0 1 X CK (MHz) 2.048 4.096 8.192 16.384 Reserved
R/W INT
I O
RXD[0--31] FSYNC
Iu I
CK
I
CKSPD[2--0]
I
TXD[0--31]
O
Transmit Data Highways 0--31. Serial TDM highway transmitting data at rates of 2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s. During external driver mode, the TXD[0--31] outputs will be continuously driven. The only exception to this is when the TEST input is asserted. When not in external driver mode, this highway can be tristated on a per-time-slot basis. See Table 41, Transmit Highway 3-State Options, on page 51 for a detailed description of all methods for 3-stating the transmit highways.
*Iu indicates internal 100 k pull-up resistor, and Id indicates 17.5 k pull-down resistor.
Lucent Technologies Inc.
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TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet February 1999
Pin Information (continued)
Table 4. TTSI2K32T Pin Descriptions (continued) Symbol TXOE[0--31] Type* O Description Transmit Output Enables 0--31. These output pins reflect the active/high-impedance status for the corresponding transmit highways. They are continuously driven to reflect the status of the output enables of the transmit highways, regardless of whether or not external driver mode is enabled via the ED (bit 6) in the general command register. The external driver for transmit highway [i] should be enabled when TXOE[i] is a 1. Also see Table 41, Transmit Highway 3-State Options, on page 51 for other methods of 3-stating the transmit highways. TDI TCK TMS TRST TDO VDD VSS VDDPLL VSSPLL NC
u
Iu I Iu Id O P P P P --
JTAG Test Data Input. JTAG Test Clock. Maximum 10 MHz. JTAG Test Mode Select. JTAG Test Reset (Active-Low). To disable the JTAG interface, tie TRST low or leave unconnected. Test Data Output. 3.3 V Supply. All VDD leads must be connected to the 3.3 V supply. Ground. 3.3 V PLL Supply. VSSPLL and VDDPLL should be decoupled with a high-speed capacitor with a value in the range of 2 F--5 F. PLL Ground. VSSPLL and VDDPLL should be decoupled with a high-speed capacitor with a value in the range of 2 F--5 F. No Connect. This pin must be left unconnected.
*I indicates internal 100 k pull-up resistor, and Id indicates internal 17.5 k pull-down resistor.
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Lucent Technologies Inc.
Preliminary Data Sheet February 1999
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Typical TSI Application
DS0 SERVICE COMPLEX HDLC FORMATTERS SYSTEM BACKPLANE (8.192 Mbits/s)
ECHO CANCELLERS
V.90 MODEMS (DSPs) T1/E1 LIU AND FRAMER ICs T7630/T7633
RX HIGHWAYS
T1/E1 LINES
T7698 T7693
T7230A TFRA08C13
TSI
MICROPROCESSOR MICROPROCESSOR BUS
5-7074(F)r.2
Figure 3. A Typical TSI Application A typical application that requires a TSI is where TDM highways that are carrying different types of data in 8-bit time slots (64 kbits/s channels) need to be switched and sent to different destinations. For example, TDM highways may contain time slots that are carrying voice, Internet traffic, signaling information, etc. The TSI could be programmed to select all the time slots, carrying Internet data from different Rx highways to be put on a another Tx highway that is connected to a bank of V.90 modems. Return data from these modems would be sent via another set of Rx highways back to the TSI, which could send the data back out over a Tx highway and to a T1 line via a T1 framer and LIU. Similarly, time slots containing signaling information which is HDLC formatted can be sent to a bank of HDLC formatters. Voice channels that have echo on them could be selectively sent to echo cancellers. Data that needs to be sent to another card in the system could be put on the system backplane via optional bus drivers.
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TX HIGHWAYS
T1/E1 LIUs
T1/E1 FRAMERS
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TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet February 1999
Interchange Fabric
The time-slot interchanger core has a memory-based architecture. The received time slots are converted from serial to parallel by the receive highways block and stored in an internal dual-ported memory called the data store, see Figure 1, Block Diagram of the TTSI2K32T on page 6. These time slots are then read out of the data store in the order specified by the connection store, converted from parallel to serial by the transmit highways section, and sent out on the transmit highways. All the time slots (bytes) coming into the device are stored in the data store. Each TDM highway can bring in up to 32 valid time slots at 2.048 Mbits/s, 64 time slots at 4.096 Mbits/s, or 128 time slots on an 8.192 Mbits/s highway, during a 125 s frame. With 16 Rx highways running at the maximum rate of 8.192 Mbits/s, the maximum capacity of the switch will be utilized. The addresses used to retreive the data from the data store are stored in the connection store. If host substituted data is to be transmitted instead of data that was received on a TDM highway, then it is stored in the connection store. Note that this device can switch any 2048 time slots from the 4096 possible recieve time-slot positions, restricted only by the data rate selection criteria for the Rx highways (see Table 6, Rx Highway Data Rate Options, on page 20). Similarily on the Tx side, this device can place the 2048 switched time slots into any of the 4096 possible transmit time-slot positions, restricted only by the Tx data rate selection criteria (see Table 7, Tx Highway Data Rate Options, on page 20). Any mode that is selected on a time-slot basis is typically made via the connection store. There are 8192 bytes in the connection store, two for each time slot that can be selected for transmission. Each one of the 4096 possible transmit time slots can be individually 3-stated. This is useful when multiple devices need to drive the same TDM highway as a bus or backplane. For extra drive, 32 individual output enables (TXOE pins) are also provided to individually control an external bus or backplane driver, one for each transmit highway. A low latency (send as soon as possible) or frame integrity (keep tagged time slots from the same highway together in the same frame) can also be selected on a time-slot basis. The user also has the option to send one of 13 predefined test patterns, a userdefined byte, or one of three user-defined idle codes, on any time slot of any Tx highway. Time slots received on any TDM highway can be easily broadcasted on any transmit highway using the connection store. If, for example, the entire connection store is filled with all zeros, this then implies low-latency mode and that the source for all transmitted data is Rx highway 0, time slot 0. Thus, the data received on RXD0 time slot 0 will end up being broadcasted on all outgoing time slots.
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Lucent Technologies Inc.
Preliminary Data Sheet February 1999
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Small and Large TSIs
The TTSI2K32T is one in a family of time-slot interchanger (TSI) devices offered by Lucent Technologies Microelectronics Group. This family of devices are all software compatible since they all have similar register maps. The larger devices of course have extra registers to configure the extra highways and also have larger connection and data stores. However, software written for a smaller TSI will run without alterations with a larger device. The TTSI2K32T and TTSI4K32T are also pin compatible, since they are in the same package. Table 5. The TSI Family Device TTSI1K16T TTSI2K32T TTSI4K32T Time-Slot Capacity 1024 2048 4096 Number of Rx/Tx Highways 16/16 32/32 32/32 Package 144-pin TQFP 217-pin PBGA 217-pin PBGA
The capacity of the TTSI1K16T can be fully utilized by receiving and/or transmitting data on all 16 highways at 4.096 Mbits/s or eight highways at 8.192 Mbits/s. Similarly, the TTSI2K32T can be fully utilized by receiving and/or transmitting data on all 32 highways at 4.096 Mbits/s or 16 highways at 8.192 Mbits/s. Other combinations of different data rates on different highways can also be used to fully utilize the TTSI1K16T and TTSI2K32T. The capacity of the TTSI4K32T is fully utilized only when data is being received and/or transmitted on all 32 highways at 8.192 Mbits/s. The TTSI4K32T can be used to make even larger switches; for example, an 8192 time-slot switch with 64 Rx and 64 Tx highways. The Rx and Tx highways of the 8K switch are labeled LRXD[0--63] and LTXD[0--63], respectively, in the figure below.
TTSI4K32T #1
TTSI4K32T #2
LRXD[0--31] LRXD[32--63]
LTXD[0--31] LTXD[32--63]
TTSI4K32T #3
TTSI4K32T #4
5-7076(F)r.1
Figure 4. An 8K Time-Slot Switch Made from 4K TSIs LRXD[0--31] are sent to both TSI #1 and #2. Similarly, LRXD[32--63] are sent to both TSI #3 and #4. The TXD[0--31] of TSI #1 are wire-ORed with the TXD[0--31] of TSI #3, to make LTXD[0--31]. Similarly, the TXD[0--31] of TSI #2 are wire-ORed with the TXD[0--31] of TSI #4, to make LTXD[32--63]. Now, if time slots on highway LRXD0 need to be switched to LTXD63, it can be done via TSI #2. The connection stores of TSI #2 and #4 must be programmed such that they both never drive their TXD31 simultaneously. The 3-state per time-slot feature of the TSI allows this to be accomplished easily.
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TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet February 1999
Microprocessor Interface
The host interface is designed to connect directly to a typical synchronous or asynchronous host bus. The interface to the TTSI2K32T includes a separate clock, PCLK, which is used only in the synchronous interface mode. This device will be a slave on the host bus and will provide the host microprocessor with the capability to read and write the TTSI2K32T address space in a minimal number of clock cycles. There is no posting of writes in the host interface, and all registers and the data and connection stores are directly accessible.
Asynchronous Mode (MM = 0)
The following two timing diagrams show read and write in the asynchronous mode.
READ DATA TSI READ ADDRESS 183 ns MAX CS AS R/W DS HIGH IMPEDANCE DT
5-6954(F).r3
D[7--0] A[14--0]
Figure 5. Asynchronous Read
D[7--0] A[14--0] CS AS R/W
TSI WRITE DATA TSI WRITE ADDRESS
183 ns MAX DS HIGH IMPEDANCE DT
5-6955(F)r.3
Figure 6. Asynchronous Write The presence of AS, CS, and DS being asserted will start the TTSI2K32T internal access. Once data has been retrieved or written, DT will be asserted indicating the TTSI2K32T is ready to terminate the access. DT will continue to be asserted until AS, CS, or DS is negated. The duration of an asynchronous read or write cycle will be a maximum of 183 ns. This duration is measured from when AS, CS, and DS are all asserted low until DT is asserted low by the TTSI2K32T.
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Lucent Technologies Inc.
Preliminary Data Sheet February 1999
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Microprocessor Interface (continued)
Synchronous Mode (MM = 1)
The following two timing diagrams show read and write in the synchronous mode.
PCLK D[7--0] A[14--0] CS AS R/W DT HIGH IMPEDANCE
5-6956(F)r.4
READ DATA READ ADDRESS
Figure 7. Synchronous Read
PCLK D[7--0] A[14--0] CS AS R/W HIGH IMPEDANCE DT
5-6957(F)r.3
WRITE DATA WRITE ADDRESS
Figure 8. Synchronous Write The synchronous write or read cycle is started when AS is sampled active with the rising edge of PCLK. In order for the TTSI2K32T to respond, CS must be active during the first or second cycle of an access depending on the value of CSV (bit 7) of the general command register. Once data has been retrieved or written, DT will be asserted for one clock, terminating the access. The duration of a synchronous read or write cycle is a combination of two periods of time. One period is the duration of the internal cycle, which will be a maximum of 160 ns. The other time period is the initiation, termination, and synchronization of activity on the processor bus, which will be a maximum of six PCLK cycles. The total duration of the cycle, from the assertion of AS to the removal of DT, will be the sum of these two periods of time. Note: The number of processor clock cycles can be reduced by one PCLK cycle if the CS input signal can be delivered soon enough to be sampled with AS and CSV (bit 7) of the general command register is set to a 1.
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TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet February 1999
Highway Data Rate Selection
The highway data rate for a particular transmit or receive highway is selected by setting HDR[1--0] (bits 1--0) in byte 2 of the highway configuration registers. All of the highways in the TTSI2K32T are grouped into pairs. RXD0 is paired with RXD1, RXD2 is paired with RXD3, . . . , and RXD30 is paired with RXD31. Similarly, TXD0 is paired with TXD1, TXD2 is paired with TXD3, . . . , and TXD30 is paired with TXD31. The maximum combined bandwidth that each pair can handle is 8.192 Mbits/s. If the programmed bandwidth of a pair exceeds 8.192 Mbits/s, one or both highways will be set to idle automatically. The register contents will not be altered to reflect this, but that particular receive or transmit highway will not carry any traffic. Table 6 shows the valid Rx highway data rate options for a particular Rx highway pair. Table 6. Rx Highway Data Rate Options RXD[2i] Data Rate (Mbits/s)* 0.000 0.000 0.000 0.000 2.048 2.048 2.048 4.096 4.096 4.096 8.192
* i = 0, 1, 2, . . . , 15.
RXD[2i + 1] Data Rate (Mbits/s)* 0.000 2.048 4.096 8.192 0.000 2.048 4.096 0.000 2.048 4.096 0.000
Table 7 shows the valid Tx highway data rate options for a particular Tx highway pair. Table 7. Tx Highway Data Rate Options TXD[2i] Data Rate (Mbits/s)* 0.000 0.000 0.000 0.000 2.048 2.048 2.048 4.096 4.096 4.096 8.192
* i = 0, 1, 2, . . . , 15.
TXD[2i + 1] Data Rate (Mbits/s)* 0.000 2.048 4.096 8.192 0.000 2.048 4.096 0.000 2.048 4.096 0.000
To meet the 8.192 Mbits/s bandwidth requirement for a transmit highway pair, a transmit highway may have to be disabled. This is done by setting its data rate to 0.000 Mbits/s and not by setting its XE bit to 0 in the transmit configuration register.
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Lucent Technologies Inc.
Preliminary Data Sheet February 1999
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Mixed-Highway Data Rates
Each receive (Rx) highway can be selected to sample at a rate of either 2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s. This rate selection is made via the HDR[1--0] field in the receive highways configuration register (byte 2). Similarly, each transmit (Tx) highway can be programmed to clock the data out at 2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s via the transmit highway configuration register (byte 2). Thus, 64 independent data rate selections can be made: 32 on the Rx side and 32 on the Tx side. Highways can also be selected to be idle, i.e., neither receiving nor transmitting data. The data rate on a receive highway does not have to match that on its corresponding transmit highway either, e.g., RXD0 and TXD0 data rates can be different. Data received on a 2.048 Mbits/s highway can be transmitted on a 4.096 Mbits/s or 8.192 Mbits/s highway too. All of this flexibility allows this device to be used to solve a variety of design problems such as data rate adaptation, etc. Many slow-speed highways can also be combined and sent out on a single high-speed highway. The figure below depicts an example where time slots are being received on different highways at different data rates and are being switched and sent out at a slower, same, or faster data rate. Each rectangle, labeled A--N, represents an 8-bit time slot.
FSYNC
RXD0 (2 Mbits/s)
A
B
RXD1 (4 Mbits/s)
C
D
E
F
RXD2 (8 Mbits/s)
G
H
I
J
K
L
M
N
TXD2 (2 Mbits/s)
G
F
TXD3 (4 Mbits/s)
D
A
K
H
TXD4 (8 Mbits/s)
J
I
C
B
N
E
M
L
5-7077(F)
Figure 9. Mixed-Highway Data Rates
Lucent Technologies Inc.
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TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet February 1999
TDM Highway Interface Timing
Virtual and Physical Frames
Figure 10 below shows a virtual frame offset from the physical frame. The FSYNC pulse marks the beginning of the physical frame, but the TSI can be programmed to interpret the location of time slot 0 at any point in a frame. Several parameters are available to make up the offset for a virtual frame with various levels of granularity. There is XTSOFF/RTSOFF for transmit/receive time-slot offsets. This offset can be up to 31 time slots for a 2.048 Mbits/s highway, 63 time slots for a 4.096 Mbits/s highway, or 127 time slots for an 8.192 Mbits/s highway. XBITOFF/ RBITOFF allow the setting of up to a 7-bit offset for transmit/receive frames. XFBOFF/RFBOFF allow fractional bit offsets of 0, 1/4, 1/2, or 3/4 bits. All of these offsets mentioned above can be independently programmed for each one of the transmit and receive highways. The maximum offset that can be introduced on an 8.192 Mbits/s highway is 127 time slots, 7 3/4 bits. The maximum offset on a 4.096 Mbits/s highway is 63 time slots and 7 3/4 bits. The maximum offset on a 2.048 Mbits/s highway is 31 time slots, 7 3/4 bits. The following examples indicate how virtual offsets can be used to simplify system designs. For example, data that is being sent to the TSI on a particular Rx highway may have incurred a several time-slot delay due to processing by HDLC formatters, echo cancellers, communication protocol processors, etc. Rather than adding an external buffer to realign all the highway data to the next FSYNC, an offset to create a virtual frame on that Rx highway can be used instead. On a transmit highway, for example, there may be a device downstream that has a processing latency of N time slots. An offset of (32 - N) time slots can be added beforehand on a 2.048 Mbits/s highway so that after processing, the TDM data is aligned to FSYNC again. Fractional bit offsets are handy for adjusting the sampling point on a Rx highway. With a 1/4-bit resolution possible, setup and hold time requirements on the Rx TDM highways for the TSI should be easily met. On transmit highways, fractional bit offsets can be used to shift the outgoing highway data slightly, so the destination device's setup and hold times can be met with adequate margins. Note that the time slot, bit, and fractional bit offsets are relative to the highway data rate and imply different durations on different speed highways. For example, a 1/4-bit offset on a 2.048 Mbits/s highway means 122 ns, on a 4.096 Mbits/s highway, it is 61 ns, and on an 8.192 Mbits/s highway, it implies a 30.5 ns offset.
FSYNC PHYSICAL FRAME, N Rx HIGHWAY Rx OFFSET Tx HIGHWAY Tx OFFSET VIRTUAL Tx FRAME, N VIRTUAL Tx FRAME, N + 1
5-7464(F)r.2
PHYSICAL FRAME, N + 1
VIRTUAL Rx FRAME, N
VIRTUAL Rx FRAME, N + 1
Figure 10. Virtual and Physical Frames
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Lucent Technologies Inc.
Preliminary Data Sheet February 1999
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
TDM Highway Interface Timing (continued)
TDM Highway Alignment at Zero Offset
The TDM highway interface logic is designed to make interconnection to the TTSI2K32T as simple as possible. Consider the timing diagram shown in Figure 11 below. Assume the following configuration register settings:
s s s s
FSYNC is active-high, FSP (bit 2) is set to 1 in the general command register. FSYNC is sampled by the rising edge of CK, FSSE (bit 1) is set to 1 in the general command register. The Tx and Rx highways are all set for zero bit and time-slot offset. The input CK speed is equal to the highway data rate.
One can see that time slot 0 of a frame coincides with the sampling of an active FSYNC. At that edge:
s s
Bit 0 of time slot 0 is latched from the Rx highway with the coincident clock. Bit 0 of time slot 0 is transmitted starting with the coincident clock.
FSYNC CK RX HIGHWAY TX HIGHWAY Rx TIME SLOT 0, BIT 0 Rx TIME SLOT 0, BIT 0 Tx TIME SLOT 0, BIT 1
5-6958(F)r.2
FSYNC SAMPLED ACTIVE Rx TIME SLOT 0 BIT 0 SAMPLE POINT
Tx TIME SLOT 0, BIT 0
Figure 11. Synchronization to FSYNC
TDM Highway Offsets
An offset may be added to the sampling of Rx time slot 0, bit 0 or the transmission of Tx time slot 0, bit 0. This can be done on any of the receive and/or transmit highways, totally independent from one another. This is done by setting the time-slot offset number, bit offset number, and fractional bit offset number on a per-highway basis using the receive and transmit highway configuration registers. To illustrate this point, consider the timing diagram shown in Figure 12 on page 24. Assume the following configuration register programming:
s s s s s
The input CK speed is set to 8.192 MHz. FSYNC is active-high, FSP (bit 2) is set to 1 in the general command register. FSYNC is sampled by the rising edge of CK, FSSE (bit 1) is set to 1 in the general command register. The RXD0 highway is set for 3/4-bit offset and a highway data rate of 4.096 Mbits/s. The TXD0 highway is set for 1-bit offset and a highway data rate of 2.048 Mbits/s.
One can see that bit 0 of the receive time slot 0 is sampled 1 and 1/2 CK cycles after FSYNC is sampled active. Since CK is set for 8.192 MHz and RXD0 is set for 4.096 Mbits/s, then 1 and 1/2 CK cycles equals 3/4 of a 4.096 Mbits/s bit period.
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TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet February 1999
TDM Highway Offsets (continued)
One can also see that bit 0 of the transmit time slot 0 is driven four CK cycles after FSYNC is sampled active. Since CK is set for 8.192 MHz and TXD0 is set for 2.048 Mbits/s, then four CK cycles equals one 2.048 Mbits/s bit period.
FSYNC
FSYNC SAMPLED ACTIVE Rx TIME SLOT 0 BIT 0 SAMPLE POINT
CK--8.192 MHz RXD0--4.096 Mbits/s (3/4-bit OFFSET) TXD0--2.048 Mbits/s (1-bit OFFSET)
TIME SLOT 63, BIT 7 TIME SLOT 31, BIT 6 TIME SLOT 0, BIT 0 TIME SLOT 31, BIT 7 TIME SLOT 0, BIT 1 TIME SLOT 0, BIT 0
5-7062(F)r.2
Figure 12. Highway Offsets
Reset Sequence
The reset sequence of the TTSI2K32T is related to the PLL operation. In order for the chip to be properly reset, the PLL must have already established a lock on the CK input signal. That event will occur 250 s after the CK input is functioning. After the PLL is locked onto the input clock, the TTSI2K32T will be in a reset state within 200 ns. This results in a reset time of 250.2 s. Subsequent resets will take 200 ns, provided CK is not interrupted. RESET is an asynchronous signal and requires no setup or hold margins relative to any other input clock or signal. After a reset, BIST must be run on the TTSI2K32T to bring all the memories in the device to a known state. This is required for correct operation of the chip. See the description below Table 17, BIST Command Register (0x02), on page 39, on how to run BIST.
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Lucent Technologies Inc.
Preliminary Data Sheet February 1999
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Low-Latency and Frame-Integrity Modes
Transmit time slots can be selected for low-latency (minimum delay) or for frame-integrity modes using the connection store memory.
Low Latency
Low latency causes a received time slot to be transmitted as soon as possible. This mode is useful for voice channels where minimum delay through the network is desirable. If the transmit (Tx) time slot is very close or before the receive (Rx) time slot, then the data will be transmitted in the next frame. If a particular transmit time slot is physically later in time than the receive time slot by a certain duration (time-slot separation), then the data will be transmitted in the current frame. The latency will be equal to the separation of the two time slots involved. The maximum latency that data can encounter through the TSI in low-latency mode is 134 s. If this latency is sufficient for a particular application, disregard any of the following details. The required separation that will cause the time slot to be transmitted in the current frame is as follows: the Tx time-slot position in the physical frame must be greater than or equal to the Rx time-slot position in the physical frame, by a duration of 2 Rx time slots + (4 + i) x 30.5176 ns, where i is the Tx highway number. When Rx and Tx highway data rates are equal and the Rx and Tx highway offsets are set to zero, the following table shows the result of the above relationship for various Tx highways. Table 8. Time-Slot Separation Required for Transmission with Minimum Latency (0 Offsets) Rx Highway Data Rate (Mbits/s) 2.048 4.096 8.192 For example:
s
Tx Highway Data Rate (Mbits/s) 2.048 4.096 8.192
Time-Slot (ts) Separation Required for Transmission in Current Frame on Highway TXD0 2 ts, 1/4 bit 2 ts, 1/2 bit 2 ts, 1 bit TXD4 2 ts, 1/2 bit 2 ts, 1 bit 2 ts, 2 bits TXD8 2 ts, 3/4 bit 2 ts, 3 bits TXD15 TXD31
2 ts, 1 1/4 bits 2 ts, 2 1/4 bits 2 ts, 4 3/4 bits 3 ts, 3/4 bits
2 ts, 1 1/2 bits 2 ts, 2 1/2 bits 2 ts, 4 1/2 bits
If data is received in time slot 0 at 2.048 Mbits/s, it could be passed through the device with minimum latency if transmitted on time slot 3 at 2.048 Mbits/s of TXD0. If data is received in time slot 1 at 4.096 Mbits/s, it could be passed through the device with minimum latency if transmitted on time slot 4 at 4.096 Mbits/s of TXD8. If data is received in time slot 2 at 8.192 Mbits/s, it could be passed through the device with minimum latency if transmitted on time slot 6 at 8.192 Mbits/s of TXD31.
s
s
If the Rx highway has an offset, then the relationship can be updated. The Rx_time-slot_position is defined as the Rx_time-slot_number + Rx_highway offset. The new relationship will determine the transmit time-slot position in the physical frame at which the received data can be transmitted with minimum delay. The new relationship is (i = Tx highway number): Tx_time-slot_position Rx_time-slot_number + Rx highway offset + 2 Rx time slots + (4 + i) x 30.5176 ns If the Tx highway also has an offset, then the relationship becomes (i = Tx highway number): Tx_time-slot_number + Tx highway offset Rx_time-slot_number + Rx highway offset + 2 Rx time slots + (4 + i) x 30.5176 ns
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TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet February 1999
Low-Latency and Frame-Integrity Modes (continued)
Low Latency (continued)
For example, consider any Rx highway running at 4.096 Mbits/s using time slot 5 to receive data, with an Rx highway offset of 3 time slots. It is to be transmitted on TXD6. The right hand side of the relationship evaluates to: 5 time slots @ 4.096 Mbits/s + 3 time slots @ 4.096 Mbits/s + 2 time slots @ 4.096 Mbits/s + (4 + 6) x 30.5176 ns 19,836.426 ns The results of the calculation show that the received data can be transmitted with minimum delay using a Tx time slot located 19,836.426 ns (or later) into the physical frame on TXD6. With a zero offset on TXD6, the time-slot number for transmission with minimum delay would be: Tx time slot 21 @ 8.192 Mbits/s Tx time slot 11 @ 4.096 Mbits/s Tx time slot 6 @ 2.048 Mbits/s
Frame Integrity
Frame integrity is applied to multiple transmit time slots in order to force data received in the same frame to be transmitted together in a subsequent frame. This rule causes added delay, but it is useful for wideband data. Such data could be ISDN BRI (2B channels) that take up two time slots on a receive highway. It could also be an ISDN H0 channel (six contiguous time slots) that is being used to carry video. The maximum latency through the device for any time slot marked for frame integrity mode is 378 s. If that latency is sufficient for a particular application, disregard any of the following details. To understand the latency involved with frame-integrity mode, consider the following information. The definition of frame integrity states that integrity is maintained between a particular Rx and Tx highway pair. This pair can be made up of any Rx highway and any Tx highway. Latency due to frame integrity mode is a function of the highway offsets of the Rx and Tx pair rather than the relative position of the time slots. Latency in this mode will be expressed in terms of physical frames. Whether time slots received in virtual Rx frame N will end up going out in virtual Tx frame N + 1, N + 2, or N + 3 is dependent on the relative highway Rx and Tx highway offsets. For a description of virtual frames, see Figure 10, Virtual and Physical Frames on page 22. Consider the following example. Assume RXD0 is switched to TXD1 with all Tx time slots marked for frame integrity (FI) on TXD1. If it is desirable to have the lowest possible latency for the data received on RXD0, then TXD1 must have a highway offset which is 3.90625 s (1 time slot @ 2.048 Mbits/s) greater than the highway offset selected for RXD0. In that case, time slots received in the virtual Rx frame (frame N) will be transmitted in the next virtual Tx frame (frame N + 1). The greatest latency will be incurred when the RXD0 offset is at least 121.09375 s (31 time slots @ 2.048 Mbits/s) greater than the offset selected for TXD1. In that case, time slots received in the current virtual Rx frame (frame N) will be transmitted three frames later, i.e., in virtual Tx frame N + 3. For all other RXD0 and TXD1 offset values, time slots received in the current virtual Rx frame will be transmitted two frames later, i.e., in virtual Tx frame N + 2.
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Lucent Technologies Inc.
Preliminary Data Sheet February 1999
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Low-Latency and Frame-Integrity Modes (continued)
Frame Integrity (continued)
The range of Rx and Tx offsets can be independently selected from 0 s to (125 - )s via the Rx and Tx highway configuration registers, bytes 0 and 1, where = 1/4 bit. The offset difference (Tx highway offset - Rx highway offset) can therefore take the range from -(125 - )s to +(125 - )s. The table below shows the virtual frame for transmission for the various cases of offset difference. Table 9. Offset Difference and Its Effect on Frame for Transmission Offset Difference = (Tx Highway Offset - Rx Highway Offset) A offset difference < B* B offset difference < C* C offset difference D*
* The values for A, B, C, and D are specified in Table 10 below.
Virtual Frame for Transmission N+3 N+2 N+1
Table 10. Offset Difference Boundaries Offset Difference Boundary A B C D Boundary Value (s) -(125 - ) -121.09375 +3.90625 +(125 - ) Boundary Value in Terms of Time Slots (ts) and Bits, at Different Data Rates 2.048 Mbits/s -(31 ts, 7 3/4 bits) -31 ts 1 ts 31 ts, 7 3/4 bits 4.096 Mbits/s -(63 ts, 7 3/4 bits) -62 ts 2 ts 63 ts, 7 3/4 bits 8.192 Mbits/s -(127 ts, 7 3/4 bits) -124 ts 4 ts 127 ts, 7 3/4 bits
Table 9 and Table 10 can be used to determine the latency of time slots through the TSI in a frame integrity situation. Keep in mind that the offset difference is the major factor in determining which virtual Tx frame the time slots will go out in. The boundary values given in Table 10 are accurate to within 1 time slot @ 8.192 Mbits/s (= 4 bits @ 4.096 Mbits/s = 2 bits @ 2.048 Mbits/s) and will depend on your particular register settings. This example can be used to determine the latency of a frame integrity situation. Keep in mind that only the Tx and Rx highway offsets are relevant when determining the number of physical frames that the transmit data will incur. However, there is a small range of offset separation where the data will go out in either virtual Tx frame N + 2 or N + 3, depending on the actual Rx and Tx offsets chosen. There may be many Rx/Tx highway pairs performing frame integrity simultaneously, but the definition of frame integrity states that integrity is maintained between each Rx and Tx pair and not across multiple receive highways. However, in practice, if a Tx highway contains FI time slots from multiple Rx highways and those Rx highways have the same highway offset, then all of the FI time slots will incur equal delay with frame integrity through the switch.
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Preliminary Data Sheet February 1999
Low-Latency and Frame-Integrity Modes (continued)
Frame Integrity (continued)
In the example shown below in Figure 13, a receive and transmit highway are both running at 2.048 Mbits/s. There are 32 time slots for each 125 s frame. The Rx and Tx highway offsets are zero. This makes the offset difference zero. Therefore, time slots selected for FI will be transmitted two frames later. The TSI is configured to perform the following switching function: Tx time slot 31 is sourced from Rx time slot 0 in low-latency mode. It goes out in frame N. Tx time slot 2 is sourced from Rx time slot 2 in low-latency mode. It goes out in frame N + 1. Tx time slot 30 is source from Rx time slot 1 in frame-integrity mode. It goes out in frame N + 2. Tx time slot 0 is sourced from Rx time slot 3 in frame-integrity mode. It goes out in frame N + 2.
FRAME B FSYNC
FRAME C
FRAME D
FRAME E
RX HIGHWAY B0 B1 B2 B3
B29 B30 B31 C0 C1 C2 C3
C29 C30 C31 D0 D1 D2 D3
D29 D30 D31 E0 E1 E2
TX HIGHWAY
Z3
A2
Z1 B0 A3
B2
A1 C0 B3
C2
B1 D0 C3
D2
5-7075(F)r.1
Figure 13. Mixed Low-Latency and Frame-Integrity Modes
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Preliminary Data Sheet February 1999
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Test-Pattern Generation
Test-pattern generation involves selecting outgoing time slots on a particular transmit highway for use in transmitting one of 15 patterns of data. The patterns available are selected using TPS[3--0] (bits 7--4) of the Test-Pattern Style Register (0x0A), Table 25 on page 44. The transmit highway and time slots involved are selected using the connection store. Using the connection store, time slots can be set for test-pattern mode and the on-chip test-pattern generator will be the source for that transmitted data. The type of test pattern used is determined by the values in the Test-Pattern Style Register (0x0A), Table 25 on page 44. Test-pattern data can be applied to any number of time slots on only one highway at a time. Any highway may be selected to transmit test-pattern data. The only restrictions for selecting the time slots set for test-pattern mode are that the time slots must be from the same highway and they must be contiguous. The sequence for enabling test-pattern generation is as follows: 1. Set TSDSM[2--0] (bits 7--5) in byte 1 of the connection store locations which correspond to the time slots involved in test-pattern substitution mode. Any range of time slots may be selected for test-pattern substitution mode, starting at any time-slot position. The remaining time slots of that highway will be unaffected. 2. Set TPS[3--0] (bits 7--4) of the Test-Pattern Style Register (0x0A), Table 25 on page 44 to select the test pattern to be sent. If a fixed user-defined byte is selected for transmission via the TPS[3--0] bits, then the TestPattern Generator Data Register (0x12), Table 33 on page 46 must also be programmed. 3. Select the data rate of the test-pattern generator via GENHDR[1--0] (bits 5--4) and set STTPG (bit 7) to 1 in the Test Command Register (0x09), Table 24 on page 43 to start transmitting a good test pattern on the selected time slots. In order for data to be transmitted, highways need to be enabled using XE (bit 2) of the Transmit Highway Configuration Register (Byte 2) (0x1002 + 4i), Table 37 on page 48 and GXE (bit 0) of the General Command Register (0x00), Table 15 on page 38. This can be done before or after the above sequence. The Tx highway that has been selected for test-pattern generation must be the only highway that has time slots selected for test-pattern substitution mode (i.e., TSDSM[2--0] = 110) in the connection store. No time slots on any other Tx highway may be selected for test-pattern substitution mode. If the Tx highway selected for test-pattern generation is changed, then the previous highway must have all its time slots that were in the TSDSM[2--0] = 110 mode, to be changed to a non-test-pattern substitution mode.
Test-Pattern Checking
Test-pattern checking involves selecting incoming time slots on a particular receive highway for reception of one of 15 test patterns. The patterns available are selected by setting CPS[3--0] (bits 3--0) of the Test-Pattern Style Register (0x0A), Table 25 on page 44. The input highway and time slots involved are selected using the following registers:
s s s
Test-Pattern Checker Highway Register (0x0B), Table 26 on page 45 Test-Pattern Checker Upper Time-Slot Register (0x0C), Table 27 on page 45 Test-Pattern Checker Lower Time-Slot Register (0x0D), Table 28 on page 45
Test-pattern data can be checked on any number of time slots on only one highway at a time. Any receive highway may be selected to check for test-pattern data. The only restriction on selecting the time slots set for testpattern checking is that the time slots must be from the same highway and they must be contiguous. The sequence for enabling test-pattern checking is as follows: 1. Set Test-Pattern Checker Highway Register (0x0B), Table 26 on page 45 to select a highway for receiving the test data.
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TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet February 1999
Test-Pattern Checking (continued)
2. Set the Test-Pattern Checker Upper Time-Slot Register (0x0C), Table 27 on page 45 and the Test-Pattern Checker Lower Time-Slot Register (0x0D), Table 28 on page 45 to indicate the range of input time slots which will be carrying test data. The range is inclusive of the time slots indicated in both registers. If only one time slot is to be selected, then the upper and lower registers should be set to the same value. 3. Set CPS[3--0] (bits 3--0) of the Test-Pattern Style Register (0x0A), Table 25 on page 44 to select the test pattern to detect. If a fixed, user-defined byte is to be detected, the CTP[7--0] bits in the Test-Pattern Checker Data Register (0x0E), Table 29 on page 45 should also be programmed with the user-defined pattern. 4. Select the data rate of the test-pattern checker via CHKHDR[1--0] (bits 3--2) and set STTPC (bit 6) in the Test Command Register (0x09), Table 24 on page 43 to prompt the checker to attempt to lock onto the selected test-pattern style. If there is a need to restart the checker (i.e., the test-pattern style has changed), then STTPC (bit 6) of the Test Command Register (0x09), Table 24 on page 43 must first be cleared to 0, and then steps 3 and 4 should be repeated. There is an interrupt register status bit related to the test-pattern checker. TPD (bit 5) of the Interrupt Status Register (0x07), Table 22 on page 41 is used to determine when, if ever, the pattern is detected. The TPD interrupt status bit will remain 0 until the pattern has been detected. This bit is cleared when read. Once TPD is set, it will not be set again until the checker is instructed to relock on the test pattern by clearing and then setting STTPC (bit 6) in the test command register.
Error Injection
The error injection feature provides the capability to inject errors into the outgoing test-pattern data. The number of errors injected is set using the Test-Pattern Error Injection Register (0x0F), Table 30 on page 45. If error injection is required, the process should start by setting up the test-pattern generator using steps 1--3 in the Test-Pattern Generation section on page 29. In order to start injecting errors into the outgoing test pattern, write the Test-Pattern Error Injection Register (0x0F), Table 30 on page 45 with the number of errors desired. When all of the errors have been injected into the outgoing data stream, the interrupt status bit BEI (bit 0) will be set in the Interrupt Status Register (0x07), Table 22 on page 41. Errors will be injected at the rate of one per time slot. Test Command Register (0x09), Table 24 on page 43 will be cleared to 0 when BEI is set.
Error Checking
Errors are checked on time slots marked for test-pattern data once the checker has locked onto the test pattern. Every time an error is detected, the ERD (bit 3) interrupt status bit is set and the test-pattern error counter register contents are incremented. There are two registers Test-Pattern Error Counter (Byte 0) (0x10), Table 31 on page 46 and Test-Pattern Error Counter (Byte 1) (0x11), Table 32 on page 46, that are used to track the number of errors detected on incoming test patterns. The error counter registers are reset after both have been read. In order to ensure that the correct value is read from these registers, byte 0 must be read first followed by byte 1. This action will latch the counter value and allow the counter logic to be reset and then continue recording.
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Preliminary Data Sheet February 1999
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
JTAG Boundary-Scan Specification
Principle of the Boundary Scan
The boundary scan (BS) is a test aid for chip, module, and system testing. The key aspects of BS are as follows: 1. Testing the connections between ICs on a particular board. 2. Observation of signals to the IC pins during normal operating functions. 3. Controlling the built-in self-test (BIST) of an IC. TTSI2K32T does not support BS-BIST. Designed according to the IEEE Std. 1149.1-1990 standard, the BS test logic consists of a defined interface: the test access port (TAP). The TAP is made up of four signal pins assigned solely for test purposes. The fifth test pin ensures that the test logic is initialized asynchronously. The BS test logic also comprises a 16-state TAP controller, an instruction register with a decoder, and several test data registers (BS register, BYPASS register, and IDCODE register). The main component is the BS register that links all the chip pins to a shift register by means of special logic cells. The test logic is designed in such a way that it is operated independently of the application logic of the TTSI2K32T (the mode multiplexer of the BS output cells may be shared). Figure 14 illustrates the block diagram of the TTSI2K32T's BS test logic.
BOUNDARY-SCAN REGISTER
CHIP KERNEL IN OUT
(UNAFFECTED BY BOUNDARY-SCAN TEST)
IDCODE REGISTER
BYPASS REGISTER TDI INSTRUCTION REGISTER TRST
MUX
TDO
TMS TCK TAP CONTROLLER
INSTRUCTION DECODER
5-3923(F)r.4
Figure 14. Block Diagram of the TTSI2K32T's Boundary-Scan Test Logic
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Preliminary Data Sheet February 1999
JTAG Boundary-Scan Specification (continued)
Test Access Port Controller
The test access port controller is a synchronous sequence controller with 16 states. The state changes are preset by the TMS, TCK, and TRST signals and by the previous state. The state changes always take place when the TCK edge rises. Figure 15 shows the TAP controller state diagram.
TRST = 0
TEST LOGIC RESET 1 0 RUN TEST/ IDLE 0 1 1 SELECT DR 0 CAPTURE DR 0 SHIFT DR 0 1 EXIT1 DR 0 PAUSE DR 1 0 EXIT2 DR 1 UPDATE DR 1 0 1 0 1 1 EXIT1 IR 0 PAUSE IR 1 0 EXIT2 IR 1 UPDATE IR 0 0 1 1 SELECT IR 0 CAPTURE IR 0 SHIFT IR 0 1
5-3924(F)r.5
Figure 15. BS TAP Controller State Diagram The value shown next to each state transition in Figure 15 represents the signal present at TMS at the time of a rising edge at TCK. The description of the TAP controller states is given in IEEE Std. 1149.1-1990 Section 5.1.2 and is reproduced in Table 11 and Table 12.
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TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
JTAG Boundary-Scan Specification (continued)
Test Access Port Controller (continued)
Table 11. TAP Controller States in the Data Register Branch Name TEST LOGIC RESET Description The BS logic is switched in such a way that normal operation of the ASIC is adjusted. The IDCODE instruction is initialized by TEST LOGIC RESET. Irrespective of the initial state, the TAP controller has achieved TEST LOGIC RESET after five control pulses at the latest when TMS = 1. The TAP controller then remains in this state. This state is also achieved when TRST = 0. Using the appropriate instructions, this state can activate circuit parts or initiate a test. All of the registers remain in their present state if other instructions are used. This state is used for branching to the test data register control. The test data is loaded in the test data register parallel to the rising edge of TCK in this state. The test data is clocked by the test data register serially to the rising edge of TCK in the state. The TDO output driver is active. This temporary state causes a branch to a subsequent state. The input and output of test data can be interrupted in this state. The test data is clocked into the second stage of the test data register parallel to the falling edge of TCK in this state.
RUN TEST/IDLE
SELECT DR CAPTURE DR SHIFT DR EXIT (1/2) DR PAUSE DR UPDATE DR
Table 12. TAP Controller States in the Instruction Register Branch Name SELECT IR CAPTURE IR SHIFT IR EXIT (1/2) IR PAUSE IR UPDATE IR Description This state is used for branching to the instruction register control. The instruction code 0001 is loaded in the first stage of the instruction register parallel to the rising edge of TCK in this state. The instructions are clocked into the instruction register serially to the rising edge of TCK in the state. The TDO output driver is active. This temporary state causes a branch to a subsequent state. The input and output of instructions can be interrupted in this state. The instruction is clocked into the second stage of the instruction register parallel to the falling edge of TCK in this state.
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TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet February 1999
JTAG Boundary-Scan Specification (continued)
Instruction Register
The instruction register (IR) is 4 bits in length. Table 13 shows the BS instructions implemented by the TTSI2K32T. Table 13. TTSI2K32T's Boundary-Scan Instructions Instruction EXTEST IDCODE HIGHZ SAMPLE/PRELOAD BYPASS EVERYTHING ELSE Code 0000 0001 0100 0101 1111 -- Act. Register TDITDO Boundary Scan Identification BYPASS Boundary Scan BYPASS BYPASS Mode TEST NORMAL X NORMAL NORMAL X Function Test external connections Read Manuf. Register 3-state Sample/load Min shift path -- Output Defined Via BS Register Core Logic Output--High Impedance Core Logic Core Logic Output--High Impedance
The instructions not supported in TTSI2K32T are INTEST, RUNBIST, and TOGGLE. A fixed binary 0001 pattern (the 1 into the least significant bit) is loaded into the IR in the CAPTURE IR controller state. The IDCODE instruction (binary 0001) is loaded into the IR during the test-logic-reset controller state and at powerup. The following is an explanation of the instructions supported by TTSI2K32T and their effect on the devices' pins. EXTEST: This instruction enables the path cells, the pins of the ICs, and the connections between ASICs to be tested via the circuit board. The test data can be loaded in the chosen position of the BS register by means of the SAMPLE/PRELOAD instruction. The EXTEST instruction selects the BS register as the test data register. The data at the function inputs is clocked into the BS register on the rising edge of TCK in the CAPTURE DR state. The contents of the BS register can be clocked out via TDO in the SHIFT DR state. The value of the function outputs is solely determined by the contents of the data clocked into the BS register and only changes in the UPDATE DR state on the falling edge of TCK. IDCODE: Information regarding the manufacturer's ID for Lucent, the IC number, and the version number can be read out serially by means of the IDCODE instruction. The IDCODE register is selected, and the BS register is set to normal mode in the UPDATE IR state. The IDCODE is loaded at the rising edge of TCK in the CAPTURE DR state. The IDCODE register is read out via TDO in the SHIFT DR state. HIGHZ: All 3-statable outputs are forced to a high-impedance state, and all bidirectional ports are forced to an input state by means of the HIGHZ instruction. The impedance of the outputs is set to high in the UPDATE IR state. The function outputs are only determined in accordance with another instruction if a different instruction becomes active in the UPDATE IR state. The BYPASS register is selected as the test data register. The HIGHZ instruction is implemented in a similar manner to that used for the BYPASS instruction. SAMPLE/PRELOAD: The SAMPLE/PRELOAD instruction enables all the input and output pins to be sampled during operation (SAMPLE) and the result to be output via the shift chain. This instruction does not impair the internal logic functions. Defined values can be serially loaded in the BS cells via TDI while the data is being output (PRELOAD).
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TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
JTAG Boundary-Scan Specification (continued)
Instruction Register (continued)
BYPASS: This instruction selects the BYPASS register. A minimal shift path exists between TDI and TDO. The BYPASS register is selected after the UPDATE IR. The BS register is in normal mode. A 0 is clocked into the BYPASS register during CAPTURE DR state. Data can be shifted by the BYPASS register during SHIFT DR. The contents of the BS register do not change in the UPDATE DR state. Please note that a 0 that was loaded during CAPTURE DR appears first when the data is being read out.
Boundary-Scan Register
The boundary-scan register is a shift register, whereby one or more BS cells are assigned to every digital TTSI2K32T pin. The TTSI2K32T's boundary-scan register bit-to-pin assignment is defined in the BSDL file, which is available upon request.
BYPASS Register
The BYPASS register is a one-stage shift register that enables the shift chain to be reduced to one stage in the TTSI2K32T.
IDCODE Register
The IDCODE register identifies the TTSI2K32T by means of a parallel, loadable, 32-bit shift register. The code is loaded on the rising edge of TCK in the CAPTURE DR state. The contents of this register is indicated in the BSDL file.
3-State Procedures
The 3-state input participates in the boundary scan. It has a BS cell, but buffer blocking via this input is suppressed for the EXTEST instruction. The 3-state input is regarded as a signal input that is to participate in the connection test during EXTEST. The buffer blocking function should not be active during EXTEST to ensure that the update pattern at the TTSI2K32T outputs does not become corrupted.
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TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet February 1999
Register Architecture
Table 14 is an overview of the register architecture. The table is a summary of the register function and address. Complete detail of each register is given in the following sections. Table 14. TTSI2K32T Register Summary Register Name/Function Reserved Connection Store Memory Reserved Data Store Memory Reserved Receive Highway 31--Reserved Receive Highway 31 Configuration Byte 2 Receive Highway 31 Configuration Byte 1 Receive Highway 31 Configuration Byte 0 ... Receive Highway 0--Reserved Receive Highway 0 Configuration Byte 2 Receive Highway 0 Configuration Byte 1 Receive Highway 0 Configuration Byte 0 Reserved Transmit Highway 31--Reserved Transmit Highway 31 Configuration Byte 2 Transmit Highway 31 Configuration Byte 1 Transmit Highway 31 Configuration Byte 0 ... Transmit Highway 0--Reserved Transmit Highway 0 Configuration Byte 2 Transmit Highway 0 Configuration Byte 1 Transmit Highway 0 Configuration Byte 0 Reserved Version Register Test-Pattern Generator Data Register Test-Pattern Error Counter Byte 1 Test-Pattern Error Counter Byte 0 Register Address (Hex) 6000--7FFF 4000--5FFF 3000--3FFF 2000--2FFF 1880--1FFF 187F 187E 187D 187C ... 1803 1802 1801 1800 1080--17FF 107F 107E 107D 107C ... 1003 1002 1001 1000 0014--0FFF 0013 0012 0011 0010
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TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Register Architecture (continued)
Table 14. TTSI2K32T Register Summary (continued) Register Name/Function Test-Pattern Error Injection Register Test-Pattern Checker Data Register Test-Pattern Checker Lower Time-Slot Register Test-Pattern Checker Upper Time-Slot Register Test-Pattern Checker Highway Register Test-Pattern Style Register Test Command Register Interrupt Mask Register Interrupt Status Register Global Interrupt Mask Register Idle Code 3 Register Idle Code 2 Register Idle Code 1 Register BIST Command Register Software Reset Register General Command Register Register Address (Hex) 000F 000E 000D 000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 0000
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TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet February 1999
Configuration Register Architecture
Note: All registers' bits default to 0 upon reset, unless noted otherwise. All TDM highway data, which is stored in the TSI, will have the following convention. Bit 7 is first transmitted and first received; bit zero is last transmitted and last received. This convention applies to the data read from the data store, the host data transmitted via the connection store, and any other configuration register which stores highway data, such as the idle code registers and the test-pattern generator data register. Table 15. General Command Register (0x00) Bit 7 Symbol CSV Name/Description Chip Select Valid. This bit is valid while the TTSI2K32T is in synchronous microprocessor interface mode only. When this bit is programmed to be 1, the chip select input pin is sampled when AS is active. When 0, chip select is latched one PCLK after AS is active. External Drivers. Used to select the use of external drivers on transmit highways. A 0 indicates that no external buffers are being used; therefore, the TXD pins will become 3-stated for time slots that are programmed as such. A 1 indicates that the TXD output highways are connected to external drivers; thus, the TXD pins will always be driven to prevent floating nodes at the inputs of the external drivers. The TXOE[0--31] outputs always reflect the high-impedance status of the corresponding TXD[0--31] highways, regardless of the ED bit setting. The only exception to this is when TEST is asserted, which 3-states all outputs. See Table 41, Transmit Highway 3-State Options, on page 51 for other methods of 3-stating the transmit highways. 5 4 -- INTOE Reserved. Read as 0. Interrupt Output Enable. This bit, when set to a 1, enables the INT output signal to be driven based on the status of the internal interrupts and their corresponding individual mask bits. When 0, the output will remain 3-stated. Interrupt Polarity. This bit defines the polarity of INT, as output from the TTSI2K32T. A 1 selects an active-low interrupt output (INT). A 0 selects an active-high interrupt output (INT), and is the default polarity. Frame Sync Polarity. This bit defines the polarity of FSYNC, as sampled by CK, which designates the beginning of the frame. A 1 selects an active-high frame synchronization (FSYNC). A 0 selects an active-low frame synchronization (FSYNC). Frame Sync Sample Edge. This bit selects the clock edge of the CK input that is used to sample the frame synchronization input. A 1 selects the rising edge; and a 0 selects the falling edge of CK. Global Transmit Enable. When 0, all 32 transmit highways are 3-stated. GXE defaults to 0 so that all outputs can be held in a high-impedance state until they have been configured and individually enabled. For other methods of 3-stating transmit highways, see Table 41, Transmit Highway 3-State Options, on page 51.
6
ED
3
INTP
2
FSP
1
FSSE
0
GXE
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Preliminary Data Sheet February 1999
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Configuration Register Architecture (continued)
Table 16. Software Reset Register (0x01) Bit 7--1 0 Symbol -- SR Reserved. Read as 0. Software Reset. Writing a 1 to this bit resets the chip. This bit has a function similar to the RESET pin. When set to 1, all registers and control logic will be initialized to their default values except the software reset register. A 0 must be written to this bit in order to clear and release the software reset. The microprocessor interface will not be affected by the software reset, and the write to this bit will terminate normally. Name/Description
Table 17. BIST Command Register (0x02) Bit 7 Symbol RB Name/Description Run BIST. Writing a 1 to this bit begins the built-in self-test for all internal memory blocks (i.e., the data and connection stores). This bit must be cleared by writing a 0 when BIST is complete. That event is indicated via the BIST complete (BC) bit in the interrupt status register, as well as the BIST done (BD) bit in the BIST command register. Writing a 0 to this bit position will also clear the BD bit. A software reset should be performed after the BIST testing sequence is complete. BIST Done (Read Only). This bit indicates when the BIST test is complete. This bit is used for polling to determine the completion of the BIST test. The real-time duration of the TSI BIST test is 2.8 seconds. This bit will remain set to a 1 reflecting the fact that the BIST is complete until the RB bit is written to a 0. BIST Pass/Fail (Read Only). This bit indicates the status of the BIST test results. A 0 indicates that no errors were detected. Reserved. Read as 0.
6
BD
5 4--0
BPF --
The BIST test sequence is performed as follows: 1. Set RB (bit 7) in the BIST command register to 1 in order to initiate the internal BIST test. 2. Wait for the BIST complete (BC) (bit 1 of the interrupt status register) interrupt to occur via the interrupt status register, if it is not masked via the interrupt mask register MASKBC bit (bit 1). Alternatively, the host can poll the BD bit in the BIST command register which will also indicate the completion of BIST. 3. Once the BIST interrupt occurs or the BD bit is set, the BPF bit in the BIST command register will reflect the BIST pass/fail result. A BPF set to 0 indicates a pass. 4. Set RB (bit 7) in the BIST command register to a 0 in order to end the internal BIST test. 5. Issue a software reset via the SR bit in the software reset register. During BIST, the TTSI2K32T will corrupt traffic and the contents of the connection store memory. The TTSI2K32T should, therefore, be taken off-line prior to running BIST and reprogrammed afterwards.
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Preliminary Data Sheet February 1999
Configuration Register Architecture (continued)
Table 18. Idle Code 1 Register (0x03) Bit 7--0 Symbol IC1 Name/Description Idle Code 1[7--0]. This register is used to identify the data to be sent on any outgoing time slot marked for idle code 1 transmission. Idle code transmission is enabled via the time-slot data select mode bits. See Table 45, Connection Store Memory (Byte 1), on page 53.
Table 19. Idle Code 2 Register (0x04) Bit 7--0 Symbol IC2 Name/Description Idle Code 2[7--0]. This register is used to identify the data to be sent on any outgoing time slot marked for idle code 2 transmission. Idle code transmission is enabled via the time-slot data select mode bits. See Table 45, Connection Store Memory (Byte 1), on page 53.
Table 20. Idle Code 3 Register (0x05) Bit 7--0 Symbol IC3 Name/Description Idle Code 3[7--0]. This register is used to identify the data to be sent on any outgoing time slot marked for idle code 3 transmission. Idle code transmission is enabled via the time-slot data select mode bits. See Table 45, Connection Store Memory (Byte 1), on page 53.
Table 21. Global Interrupt Mask Register (0x06) Bit 7--1 0 Symbol -- GIE Reserved. Read as 0. Global Interrupt Enable. This bit must be written to a 1 in order for INT to be asserted as a result of the possible interrupt conditions. This is in addition to the mask bits in the interrupt mask register. When 0, the INT output is blocked independent of the programming of the interrupt mask register. When 1, the INT output is enabled and will be asserted based on the interrupt status and mask bits. Name/Description
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TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Configuration Register Architecture (continued)
Table 22. Interrupt Status Register* (0x07) Bit 7 6 Symbol -- FSERR Reserved. Read as 0. Frame Sync Error. When set to 1, this bit indicates that an error related to frame sync has occurred. This error could be a result of a missing FSYNC or a misaligned FSYNC. Test Pattern Detected. The TPD bit indicates the state of the test-pattern checker. When TPD = 0, the test-pattern checker has not yet located the selected test pattern. When TPD = 1, the test-pattern checker has located the selected test pattern. Test-pattern data must be error-free for 32 time slots before it is considered detected. If 32 or more time slots are selected for test-pattern checking, this event could occur within one 125 s frame. If only two time slots are selected for test-pattern checking, then the test pattern will be detected after 16 frames. Reserved. Read as 0 or 1. Error Detected. This bit is set to 1 each time an error has been detected in the test pattern once the test pattern has first been detected. Reserved. Read as 0. BIST Complete. When set to 1, this status bit indicates that the BIST sequence is complete. Bit Errors Inserted. When set to 1, this status bit indicates that the request to insert bit errors into the outgoing test pattern is complete. Name/Description
5
TPD
4 3 2 1 0
* Read-only register.
-- ERD -- BC BEI
This register is clear on read. Once the status bits are read, they will remain cleared until the next interrupt event occurs. The interrupt mask register in combination with the global interrupt enable GIE (bit 0) in the global interrupt mask register determines when the INT pin gets asserted when an interrupt status bit gets set. In general, the interrupt status register bits will update regardless of the mask bits. The exception to this is the FSERR bit, which will not be set if the corresponding mask bit is set.
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Configuration Register Architecture (continued)
Table 23. Interrupt Mask Register (0x08) Bit 7 6 Symbol -- MASKFS Reserved. Read as 0. Mask Frame Sync Error Interrupt. Set this bit to a 1 to mask the generation of an interrupt as a result of a frame sync error. Resets to a 1, which prevents the status bit from generating an interrupt. Setting this bit to a 1 also prevents the detection of a frame sync error and, thus, the setting of the FSERR bit in the interrupt status register. This is done to prevent an unintended interrupt at the first FSYNC pulse after the reset sequence. Mask Test-Pattern Detection Interrupt. Set this bit to a 1 to mask the generation of an interrupt as a result of a test-pattern detection. Resets to a 1, which prevents the status bit from generating an interrupt. Reserved. Read as 1. Always write a 1 to this bit when writing this register. Mask Error Detected Interrupt. Set this bit to a 1 to mask the generation of an interrupt as a result of a single bit error detected in the incoming test pattern. Resets to a 1, which prevents the status bit from generating an interrupt. Reserved. Read as 1. Always write a 1 to this bit when writing this register. Mask BIST Complete Interrupt. Set this bit to a 1 to mask the generation of an interrupt as a result of completing the memory BIST. Resets to a 1, which prevents the status bit from generating an interrupt. Mask Bit Errors Inserted Interrupt. Set this bit to a 1 to mask the generation of an interrupt as a result of completing the insertion of all requested bit errors. Resets to a 1, which prevents the status bit from generating an interrupt. Name/Description
5
MASKTPD
4 3
-- MASKERD
2 1
-- MASKBC
0
MASKBEI
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Configuration Register Architecture (continued)
Table 24. Test Command Register (0x09) Bit 7 Symbol STTPG Name/Description Start Test-Pattern Generator. Writing a 1 to this register will cause the generator to start generating a test pattern based on the pattern indicated in the testpattern style register. Writing a 0 to this register will stop the test-pattern generation and provide the opportunity to change the test-pattern style. Start Test-Pattern Checker. Writing a 1 to this register will cause the checker to start locking on to a test pattern based on the pattern indicated in the testpattern style register. Writing a 0 to this register will stop the test-pattern checking and provide the opportunity to change the test-pattern style. Test-Pattern Generator Highway Data Rate. These bits are used to indicate the highway data rate of the transmit highway selected for test-pattern generation. It must match the Tx highway data rate which was set in transmit highway configuration register (byte 2), HDR[1--0] bits. The transmit highway selection for test-pattern generation is done using the connection store. Only one highway at a time can be involved with test-pattern generation. Test-pattern generation and checking does not affect the operation of other time slots or highways. GENHDR1 0 0 1 1 3--2 CHKHDR [1--0] GENHDR0 0 1 0 1 2.048 Mbits/s (default) 4.096 Mbits/s 8.192 Mbits/s 0.000 Mbits/s (idle, not transmitting data)
6
STTPC
5--4
GENHDR [1--0]
Test-Pattern Checker Highway Data Rate. These bits are used to indicate the highway data rate of the receive highway selected for test-pattern checking. It must match the Rx highway data rate which was set in receive highway configuration register (byte 2), HDR[1--0] bits. The transmit highway selection for testpattern generation is done using the test-pattern checker highway register. Only one highway at a time can be involved with test-pattern checking. Test-pattern generation and checking does not affect the operation of other time slots or highways. CHKHDR1 0 0 1 1 CHKHDR0 0 1 0 1 2.048 Mbits/s (default) 4.096 Mbits/s 8.192 Mbits/s 0.000 Mbits/s (idle, not receiving data)
1--0
--
Reserved. Read as 0.
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Configuration Register Architecture (continued)
Table 25. Test-Pattern Style Register (0x0A) Bit 7--4 Symbol TPS[3--0] Name/Description Generator Test-Pattern Style[3--0]. These 4 bits determine the type of test pattern that will be generated by the on-line maintenance test-pattern generator. TPS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 TPS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 TPS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 TPS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Test-Pattern Description MARK (all 1s) (AIS - red alarm) QRSS (220 - 1 with zero suppression) (O.151) 31(25 - 1) PRBS 63(26 - 1) PRBS 511(29 - 1) PRBS (O.153) 511(29 - 1) PRBS (reversed) 2047(211 - 1) PRBS (O.152) 2047(211 - 1) PRBS (reversed) 215 - 1 PRBS (O.151) (noninverted) 220 - 1 PRBS (O.153) 220 - 1 PRBS (reversed) 223 - 1 PRBS (V.33) (noninverted) 1:1 (alternating 1s and 0s). Reserved. Reserved. Fixed. User-defined byte, stored in the testpattern generator data register will be sent.
PRBS = pseudorandom binary sequence. QRSS = quasi-random signal source. 3--0 CPS[3--0] Checker Test-Pattern Style[3--0]. These 4 bits determine the type of test pattern that will be detected by the on-line maintenance test-pattern checker. CPS3 CPS2 CPS1 CPS0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Test-Pattern Description MARK (all 1s) (AIS - red alarm) QRSS (220 - 1 with zero suppression) (O.151) 31(25 - 1) PRBS 63(26 - 1) PRBS 511(29 - 1) PRBS (O.153) 511(29 - 1) PRBS (reversed) 2047(211 - 1) PRBS (O.152) 2047(211 - 1) PRBS (reversed) 215 - 1 PRBS (O.151) (noninverted) 220 - 1 PRBS (O.153) 220 - 1 PRBS (reversed) 223 - 1 PRBS (V.33) (noninverted) 1:1 (alternating 1s and 0s). Reserved. Reserved. Fixed. The checker will compare against the userdefined byte, stored in the test-pattern checker data register.
PRBS = pseudorandom binary sequence. QRSS = quasi-random signal source.
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Configuration Register Architecture (continued)
Table 26. Test-Pattern Checker Highway Register (0x0B) Bit 7--5 4--0 Symbol -- CHS[4--0] Reserved. Checker Highway Select[4--0]. These 5 bits determine the receive highway to which the test-pattern checker is connected. Name/Description
Table 27. Test-Pattern Checker Upper Time-Slot Register (0x0C) Bit 7 6--0 Symbol -- Reserved. Name/Description
CKRUP[6--0] Checker Upper Time-Slot Select[6--0]. These 7 bits determine the upper time slot in the input highway to which the test-pattern checker is connected. All contiguous time slots that lie between the lower and upper time-slot boundaries inclusive are monitored for the test pattern. The range of time slots that can be monitored is from 1 time slot to the entire span (32, 64, and 128 time slots for a 2.048 Mbits/s, 4.096 Mbits/s, 8.192 Mbits/s highway, respectively). If one time slot is to be monitored, then CKRUP and CKRLOW should be set to the same value.
Table 28. Test-Pattern Checker Lower Time-Slot Register (0x0D) Bit 7 6--0 Symbol -- CKRLOW [6--0] Reserved. Checker Lower Time-Slot Select[6--0]. These 7 bits determine the lower time slot in the input highway to which the test-pattern checker is connected. All contiguous time slots that lie between the lower and upper time-slot boundaries inclusive are monitored for the test pattern. The range of time slots that can be monitored is from 1 time slot to the entire span (32, 64, and 128 time slots for a 2.048 Mbits/s, 4.096 Mbits/s, 8.192 Mbits/s highway, respectively). If one time slot is to be monitored, then CKRUP and CKRLOW should be set to the same value. Name/Description
Table 29. Test-Pattern Checker Data Register (0x0E) Bit 7--0 Symbol CTP[7--0] Name/Description Checker Test Pattern[7--0]. The data written here will be used for comparison when the fixed mode is programmed into the test-pattern style register.
Table 30. Test-Pattern Error Injection Register (0x0F) Bit 7--0 Symbol BEC[7--0] Name/Description Bit Error Count[7--0]. This register is used to indicate the number of single bit errors that are to be injected into the outgoing test pattern (QRSS, PRBS, or fixed user-defined byte). This register can be programmed to inject up to 255 bit errors. The BEI bit in the interrupt status register will indicate when all of the errors have been injected. BEC[7--0] will automatically be reset when BEI is set. In order to send out additional errors, BEC[7--0] should be rewritten. Errors are injected at the rate of one per time slot.
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Configuration Register Architecture (continued)
Table 31. Test-Pattern Error Counter (Byte 0) (0x10)* Bit 7--0
* Read-only register.
Symbol EC[7--0]
Name/Description Error Counter[7--0]. Least significant bits of 16-bit error counter. See note below for resetting counter.
Table 32. Test-Pattern Error Counter (Byte 1) (0x11)* Bit 7--0
* Read-only register.
Symbol EC[15--8]
Name/Description Error Counter[15--8]. Most significant bits of 16-bit error counter. See note below for resetting counter.
Note: The error counter will be incremented each time a bit error is detected by the pattern checker. In order to ensure that the correct value is read from these registers, byte 0 must be read first followed by byte 1. This action will latch the error counter value and allow the counter to be reset and continue recording as time proceeds. Table 33. Test-Pattern Generator Data Register (0x12) Bit 7--0 Symbol GTP[7--0] Name/Description Generator Test Pattern[7--0]. The data written here will be sent out repeatedly if the fixed data test-pattern mode is selected in the test-pattern style register.
Table 34. Version Register (0x13)* Bit 7--2 1--0 Symbol -- VER[1--0] Reserved. Version Number. Read as 00. Name/Description
* Read-only register. Reading a 00 from this register indicates version number 1.0.
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Configuration Register Architecture (continued)
Table 35. Transmit Highway Configuration Register (Byte 0) (0x1000 + 4i)* Bit 7 6--4 Symbol -- XBITOFF [2--0] Reserved. Read as 0. Transmit Highway Bit Offset[2--0]. XBITOFF is used to offset the beginning of an outgoing frame by the indicated number of bit times. If no bit offsets are required, these bits should be set to 000. The following list shows the effect of setting these bits. 000 = no bit offset 001 = 1-bit offset 010 = 2-bit offset ... 111 = 7-bit offset Note: Bit periods are relative to the highway data rate set for each highway. XTSOFF, XBITOFF, and XFBOFF are used in conjunction to define the start of the outgoing frame. The values are added together to position the sampling of time slot 0, bit 0 for each highway. 3--2 XFBOFF [1--0] Transmit Highway Fractional Bit Offset[1--0]. XFBOFF is used to offset the beginning of an outgoing frame by the indicated number of fractional bit times. If no fractional bit offsets are required, these bits should be set to 00. The following list shows the effect of these bits. 00 = no fractional bit offset 01 = 1/4-bit fractional offset 10 = 1/2-bit fractional offset 11 = 3/4-bit fractional offset Note: Bit periods are relative to the highway data rate set for each highway. XTSOFF, XBITOFF, and XFBOFF are used in conjunction to define the start of the outgoing frame. The values are added together to position the sampling of time slot 0, bit 0 for each highway. 1--0 -- Reserved. Must be written to 00.
* i = the transmit highway number.
Name/Description
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Configuration Register Architecture (continued)
Table 36. Transmit Highway Configuration Register (Byte 1) (0x1001 + 4i)* Bit 7 6--0 Symbol -- XTSOFF [6--0] Reserved. Read as 0. Transmit Highway Time-Slot Offset[6--0]. XTSOFF is used to offset the beginning of an outgoing frame by the indicated number of time slots (bytes). If no time-slot offsetting is required, these bits should be set to zero. The following table shows the range of offsets for the different highway data rates. Highway Data Rate 2.048 Mbits/s 4.096 Mbits/s 8.192 Mbits/s Time-Slot Offset Range 0--31 0--63 0--127 Name/Description
Note: A time slot is always 8 bits. A bit period is relative to the highway data rate set for each highway. XTSOFF, XBITOFF, and XFBOFF are used in conjunction to define the start of the outgoing frame. The values are added together to position the transmission of time slot 0, bit 0.
* i = the transmit highway number.
Table 37. Transmit Highway Configuration Register (Byte 2) (0x1002 + 4i)* Bit 7--3 2 Symbol -- XE Reserved. Read as 0. Transmit Highway 3-State Enable. The associated output highway is high impedance when this bit is 0 (default after reset). When this bit is set to 1, the output driver is enabled. The effect of this bit is dependent on the status of the external drive bit of the general command register. See Table 15, General Command Register (0x00), on page 38 for details. For other methods of 3-stating transmit highways, see Table 41, Transmit Highway 3-State Options, on page 51. Transmit Highway Data Rate[1--0]. HDR1 HDR0 0 0 2.048 Mbits/s (default) 0 1 4.096 Mbits/s 1 0 8.192 Mbits/s 1 1 0.000 Mbits/s (idle, not transmitting data) All of the transmit highways are grouped into pairs. TXD0 with TXD1, TXD2 with TXD3, . . . , and TXD30 with TXD31. The maximum combined bandwidth for each pair is 8.192 Mbits/s. Refer to Table 7, Tx Highway Data Rate Options, on page 20 for highway rate combination.
* i = the transmit highway number.
Name/Description
1--0
HDR[1--0]
Note: During CK input interruptions (e.g., clock switching), the transmit highways should be 3-stated by clearing the GXE (bit 0) of the general command register. The highways can be enabled by writing a 1 to the GXE bit once the PLL has regained lock (250 s later).
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Configuration Register Architecture (continued)
Table 38. Receive Highway Configuration Register (Byte 0) (0x1800 + 4i)* Bit 7 6--4 Symbol -- RBITOFF [2--0] Reserved. Read as 0. Receive Highway Bit Offset[2--0]. RBITOFF is used to offset the beginning of an incoming frame by the indicated number of bit times. If no bit offsets are required, these bits should be set to 000. The following list shows the effect of setting these bits. 000 = no bit offset 001 = 1-bit offset 010 = 2-bit offset ... 111 = 7-bit offset Note: Bit periods are relative to the highway data rate set for each highway. RTSOFF, RBITOFF, and RFBOFF are used in conjunction to define the start of the incoming frame. The values are added together to position the sampling of time slot 0, bit 0 for each highway. 3--2 RFBOFF [1--0] Receive Highway Fractional Bit Offset[1--0]. RFBOFF is used to offset the beginning of an incoming frame by the indicated number of fractional bit times. If no fractional bit offsets are required, these bits should be set to 00. The following list shows the effect of these bits. 00 = no fractional bit offset 01 = 1/4-bit fractional offset 10 = 1/2-bit fractional offset 11 = 3/4-bit fractional offset Note: Bit periods are relative to the highway data rate set for each highway. RTSOFF, RBITOFF, and RFBOFF are used in conjunction to define the start of the incoming frame. The values are added together to position the sampling of time slot 0, bit 0 for each highway. 1--0 -- Reserved. (Read/Write) Must be written to 00.
* i = the receive highway number.
Name/Description
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Configuration Register Architecture (continued)
Table 39. Receive Highway Configuration Register (Byte 1) (0x1801 + 4i)* Bit 7 6--0 Symbol -- RTSOFF [6--0] Reserved. Read as 0. Receive Highway Time-Slot Offset[6--0]. RTSOFF is used to offset the beginning of an incoming frame by the indicated number of time slots (bytes). If no time-slot offsetting is required, these bits should be set to zero. The following table shows the range of offsets for the different highway data rates. Highway Data Rate 2.048 Mbits/s 4.096 Mbits/s 8.192 Mbits/s Time-Slot Offset Range 0--31 0--63 0--127 Name/Description
Note: A time slot is always 8 bits. A bit period is relative to the highway data rate set for each highway. RTSOFF, RBITOFF, and RFBOFF are used in conjunction to define the start of the incoming frame. The values are added together to position the sampling of time slot 0, bit 0.
* i = the receive highway number.
Table 40. Receive Highway Configuration Register (Byte 2) (0x1802 + 4i)* Bit 7--3 2 Symbol -- LC Reserved. Read as 0. Loopback Control. This bit is used to control the internal loopback of the TXD highway to the corresponding RXD highway. When set to 1, the TXD highway as input to this RXD highway. The transmit highway involved will be internally looped back to the matching receive highway so that the TXD[i] output is now the input to RXD[i]. When a particular highway is in this mode, the receive highway offset must be 1/2-bit greater than the corresponding transmit highway offset. When LC is cleared to 0, the RXD pin is the source of highway data (default). Receive Highway Data Rate[1--0]. HDR1 HDR0 0 0 2.048 Mbits/s (default) 0 1 4.096 Mbits/s 1 0 8.192 Mbits/s 1 1 0.000 Mbits/s (idle, not receiving data) All of the receive highways are grouped into pairs. RXD0 with RXD1, RXD2 with RXD3, . . . , and RXD30 with RXD31. The maximum combined bandwidth for each pair is 8.192 Mbits/s. Refer to Table 6, Rx Highway Data Rate Options, on page 20 for highway rate combination. Name/Description
1--0
HDR[1--0]
* i = the receive highway number.
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Configuration Register Architecture (continued)
Transmit Highway 3-State Options
There are several ways of 3-stating the transmit highways: TEST (active-low) is the input pin that 3-states all outputs and bidirectional pins of the device. GXE (bit 0) (active-high) is the global transmit enable bit in the general command register. It applies to all transmit highways. XE (bit 2) (active-high) is the transmit highway 3-state enable bit in the transmit highway configuration register (byte 2). There is a separate XE bit for each one of the 32 transmit highways. ED (bit 6) (active-high) is the external drivers bit in the general command register. This bit applies to all the transmit highways. It affects the 3-stating of the transmit highways. Time slots that are selected to be 3-stated, by setting the TSDSM[2--0] bits to 0x7 in byte 2 of the connection store, will be driven with random data if ED = 1. Otherwise, these time slots will be 3-stated. Table 41. Transmit Highway 3-State Options TEST GXE (Input (Cfg Bit) Pin) 0 1 1 1 1 X 0 0 1 1 ED XE for (Cfg Transmit Bit) Highway [i] (Cfg Bit) X 0 1 0 0 X X X 0 1 TXD[0--31] Pins TXOE[0--31] Pins
All high impedance. All high impedance. All driven with random data. TXD[i] = high impedance. TXD[i] = 0, 1, or high impedance according to connection store programming. TXD[i] is driven with random data. TXD[i] = 0 or 1 reflecting the correct transmit data. Time slots which are selected for high-impedance mode via the connection store will be driven with random data and not 3-stated.
All high impedance. All 0. All 0. TXOE[i] = 0. TXOE[i] = 0 or 1, representing high-impedance state according to connection store programming. TXOE[i] = 0. TXOE[i] = 0 or 1, representing high-impedance state according to connection store programming.
1 1
1 1
1 1
0 1
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Data Store Memory
Microprocessor access to the incoming highway data is provided by directly reading the data store memory. Each one of the time slots is addressable by constructing the address in the following way. Microprocessor reads to this address space will occur immediately. Microprocessor writes to this address space will not change the contents of the data store. If user data is to be sent out on a particular time slot, the host data substitution mode in the connection store should be used. Table 42. Address Scheme for Data Store Memory Data Store Memory Address 14 0 13 1 12 0 11 10 9 8 7 6 5 4 3 2 1 0
Receive Highway Number (0--31)
Receive Time-Slot Address (0--127)
To illustrate the addressing scheme, consider the following examples: To read the data received in time slot 7 on RXD6, the following address is used to access the TSI data store memory location. A[14--0] = 010_00110_0000111 = 0x2307 Note: All TDM highway data which is stored in the TSI will have the following convention. The most significant bit of a byte is first transmitted and first received, the least significant bit is last transmitted and last received. This convention applies to the data read from the data store, the host data transmitted via the connection store, and any other configuration register that stores highway data.
Connection Store Memory
The connection store memory is primarily used to set up the switching matrix and selects the transmit data source for each one of the outgoing time slots. There are two connection store byte locations associated with each one of the outgoing time slots. The address for each of the corresponding connection store memory locations is constructed in the following way. Table 43. Address Scheme for Connection Store Memory Connection Store Memory Address 14 1 13 0 12 11 10 9 8 7 6 5 4 3 2 1 0 Byte 0, 1 Select
Transmit Highway Number (0--31)
Transmit Time-Slot Address (0--127)
If any particular transmit highway is not programmed to use the total available bandwidth (8.192 Mbits/s), then the connection store memory locations representing the unused time slots are not used. For example, assume highway 7 is set for a highway data rate of 4.096 Mbits/s. This translates to a total of 64 time slots being transmitted on highway 7. In that case, addresses A[14--0] = 0x4700--0x477F must be set. Addresses A[14--0] = 0x4780-- 0x47FF are irrelevant for a 4.096 Mbits/s highway and need not be set. The connection store memory does not have a default state. Therefore, after powerup, the relevant locations in the connection store must be programmed. However, the connection store contents are not affected by a software or hardware reset of the TTSI2K32T.
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Connection Store Memory (continued)
Table 44. Connection Store Memory (Byte 0) Bit 7--0 Symbol RTSA[6--0]/ HSD[7--0] Name/Description Receive Time-Slot Address[6--0]/Host Substituted Data[7--0]. If lowlatency or frame-integrity time-slot data select modes are selected for the particular transmit time slot being configured, then these bits are used to indicate the receive time-slot address from which the transmit time-slot data is sourced. Bit 7 should be set to 0. If the host data substitution mode is selected for the particular transmit time slot being configured, then these 8 bits will represent the data byte to be transmitted. These bits are not valid for time-slot data select modes 3--7. Table 45. Connection Store Memory (Byte 1) Bit 7--5 Symbol Name/Description
TSDSM[2--0] Time-Slot Data Select Mode[2--0] 0 0 0 Low-latency mode. 0 0 1 Frame-integrity mode. 0 1 0 Host data substitution mode. 0 1 1 Idle code 1 substitution mode. 1 0 0 Idle code 2 substitution mode. 1 0 1 Idle code 3 substitution mode. 1 1 0 Test-pattern substitution mode--test pattern is selected via test-pattern style register. 1 1 1 High-impedance mode. RXHWY [4--0] Receive Highway Number. Used to select the receive highway from which the outgoing time-slot data is sourced. These bits are only valid for time-slot data select modes 0 and 1.
4--0
To illustrate the connection store programming scheme, consider the following example: To configure the transmission of time slot 7 on TXD6, the following addresses are used to access the relevant TSI connection store memory locations. A[14--0] = 10_00110_0000111_0 = 0x460E--to access byte 0 A[14--0] = 10_00110_0000111_1 = 0x460F--to access byte 1 Now, if it is desired to send Rx time slot 4 from RXD3 to time slot 7 on TXD6 in frame integrity mode, then the following data should be written to the above addresses. Data byte 0 = 0_0000100 = 0x04 Data byte 1 = 001_00011 = 0x23 Thus, to map Rx time slot 4 from RXD3 to Tx time slot 7 on TXD6, in frame integrity mode, the following two TSI writes must be performed. Write location 0x460E with 0x04 Write location 0x460F with 0x23
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Connection Store Memory (continued)
TSDSM[5--0] (bits 7--5) of byte 1 of the connection store select the source of data for each of the time slots being transmitted by the TTSI2K32T. The configuration can be divided into three groups. Group 1 Low-Latency Mode. For the time slots marked as low latency, the transmit data will be retrieved from the data store based on the programming of TSA[6--0] (bits 6--0) of byte 0 and RXHWY[4--0] (bits 4--0) of byte 1. Bit 7 of byte 0 is ignored. When each of the individual transmit time slots are retrieved from the data store memory for transmission, the most recent copy of the receive time slot will be fetched resulting in a latency that never exceeds 134 s. This is the maximum latency for lowlatency mode independent of highway configurations (e.g., highway speed, clock speed, offsets, etc.). Refer to the Low-Latency and Frame-Integrity Modes section on page 25 for a detailed description of the latency calculation. Frame-Integrity Mode. For the time slots marked as frame integrity, the transmit data will be retrieved from the data store based on the programming of TSA[6--0] (bits 6--0) of byte 0 and RXHWY[4--0] (bits 4--0) of byte 1. Bit 7 of byte 0 is ignored. Any number of time slots from any number of transmit highways can be marked for frame integrity. When each of the individual transmit time slots marked for frame integrity are retrieved from the data-store memory for transmission, the internal controller ensures that they are chosen from a receive frame which has already been entirely stored in the data store, thereby ensuring frame integrity. Refer to the Low-Latency and Frame-Integrity Modes section on page 25 for a detailed description of the actual latency incurred through the device. Group 2 Host-Data Substitution Mode. This mode also provides the means to transmit host-supplied data repeatedly onto any or all of the 2048 transmit time slots; however, the data to be substituted is stored in HSD[7--0] (bits 7--0) of byte 0 for each transmit time slot. RXHWY[4--0] (bits 4--0) of byte 1 are ignored in this mode. Host-data mode can be used to customize the data for each of the 2048 transmit time slots. When a time slot is configured for host-data substitution mode, the data written to byte 0 of the connection store will have the following convention. Bit 7 is first transmitted, and bit 0 is last transmitted. Idle-Code Substitution Mode. These three idle-code substitution modes provide the means to transmit microprocessor data repeatedly onto any or all of the 2048 transmit time slots. Three idle-code registers (separate from the connection store memory) provide the capability to repeatedly broadcast three different programmed values to any or all time slots set for idle-code substitution mode. When programming idle-code substitution mode, only the TSDSM[2--0] (bits 7--5) of byte 1 for all of the transmit time slots involved needs to be written. Byte 0 and RXHWY[4--0] (bits 4--0) of byte 1 are both ignored. Test-Pattern Substitution Mode. This mode is also used to substitute alternative transmit data rather than use the receive time slots being stored in the data store. Since the test-pattern selection is done outside of the connection store, only TSDSM[2--0] (bits 7--5) of byte 1 for each of the time slots involved needs to be programmed. Byte 0 and RXHWY[4--0] (bits 4--0) of byte 1 are both ignored. The test-pattern selection and usage rules are described in the Test-Pattern Generation section on page 29. Group 3 High-Impedance Mode. This mode is used to 3-state any of the 2048 transmit time slots on an individual basis. For example, consider the case where an 8.192 Mbits/s highway is shared by four devices, each having one-fourth of the total bandwidth. If the TTSI2K32T were allocated time slots 64--95, then high-impedance mode would be set for time slots 0--63 and 96--127. Time slots 64--95 could be set to any combination of the eight possible modes. When programming the high-impedance mode, only TSDSM[2--0] (bits 7--5) of byte 1 for all of the transmit time slots involved needs to be written. Connection store byte 0 and RXHWY[4--0] (bits 4--0) of byte 1 are both ignored.
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Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of this data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. External leads can be safely soldered or bonded at temperatures up to 300 C. Parameter Storage Temperature Voltage on Any Pin with Respect to Ground Power Dissipation Symbol Tstg VIN PD Min -65 -0.5 -- Max 125 5.8* 440 Unit C V mW
* This maximum rating only applies when the device is powered up with VDD.
Operating Conditions
Parameter Power Supply Low-level Input Voltage High-level Input Voltage Ambient Operating Temperature Range Symbol VDD VIL VIH TA Min 2.97 -- 2.1 -40 Max 3.63 0.8 5.8 85 Unit V V V C
Handling Precautions
Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Lucent employs a human-body model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been adopted for the CDM. However, a standard HBM (resistance = 1500 , capacitance = 100 pF) is widely used and, therefore, can be used for comparison. The HBM ESD threshold presented here was obtained by using these circuit parameters: Human-Body Model ESD Threshold Device Voltage TTSI2K32T >1000 V
Lucent Technologies Inc.
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TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet February 1999
Electrical Characteristics
TA = -40 C to +85 C; VDD = 3.3 V 10%; VSS = 0 V Parameter Input Leakage Current: Non-pull-up Pins Pull-up Pins Non-pull-up I/O Pins Pull-down Pins Output Voltage: Low: DT, D[7--0] TXD[31--0], TXOE[31--0] TDO, INT High: DT, D[7--0] TXD[31--0], TXOE[31--0] TDO, INT Load Capacitance: DT, D[7--0], INT TXD[31--0] TXOE[31--0] TDO Symbol IIL IIL IIL IIL VOL IOL = -10 mA IOL = -6 mA IOL = -2 mA VOH IOH = 10 mA IOH = 6 mA IOH = 2 mA CL CL CL CL -- -- -- -- 2.4 2.4 2.4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 50 25 20 70 V V V pF pF pF pF -- -- -- -- -- -- 0.4 0.4 0.4 V V V Test Conditions VSS < VIN < VDD 10% VIN = VSS VSS < VIN < VDD 10% VIN = VDD 10% Min -- -- -- -- Typ -- -- -- -- Max 10 60 70 300 Unit A A A A
Timing Characteristics
TA = -40 C to +85 C; VDD = 3.3 V 10%; VSS = 0 V The following timing characteristics are generated for the TTL input and output levels. Table 46. Clock Specifications Pin Name PCLK CK Frequency 0 MHz--65 MHz 2.048 MHz 4.096 MHz 8.192 MHz 16.384 MHz 10 MHz Duty Cycle 50% 10% 50% 10% 50% 10% 50% 10% 50% 10% 50% 10% Clock Period Stability -- 64 ns 32 ns 16 ns 8 ns -- Rise Time (max) -- 10 ns 10 ns 10 ns 10 ns -- Fall Time (max) -- 10 ns 10 ns 10 ns 10 ns --
TCK
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Lucent Technologies Inc.
Preliminary Data Sheet February 1999
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Timing Characteristics (continued)
A[14--0] R/W t3 CS t5 AS t1 DS t4 DT HIGH IMPEDANCE t8 D[7--0]
READ DATA
5-7063(F)r.2
READ ADDRESS
t2
t4
Figure 16. Asynchronous Read Cycle Timing Using DT Handshake
A[14--0] R/W CS AS t1 DS DT t6 HIGH IMPEDANCE
WRITE ADDRESS
t2 t3 t5 t4 t4 t7 D[7--0]
WRITE DATA
5-7064(F)r.2
Figure 17. Asynchronous Write Cycle Timing Using DT Handshake Table 47. Asynchronous Read and Write Interface Timing Using DT Handshake Symbol t1 t2 t3 t4 t5 t6 t7 t8 Description A[14--0] or R/W Setup to AS A[14--0] or R/W Hold from AS CS Hold from AS or DS DT Output Delay from AS or DS (CL = 50 pF) DT or D[7--0] High-impedance from CS (CL = 50 pF) D[7--0] Input Setup to DS (CL = 50 pF) D[7--0] Input Hold from DS (CL = 50 pF) D[7--0] Output Setup Prior to DT Output (CL = 50 pF) Min 0 0 4* 3* -- 0 0 0 Max -- -- -- 8* 8.5* -- -- -- Unit ns ns ns ns ns ns ns ns
* CS asynchronously controls the output enable of D[7--0] and DT. The delay from CS to the output enable of DT is equivalent to the delay from AS or DS to DT. Therefore, in order to guarantee that DT is driven high before being 3-stated, a CS hold time is required (t3). If this timing cannot be met, then there are two options. One, disconnect DT and rely on wait-states to terminate the cycle. The read or write cycle will be completed by the device 183 ns after the start of the cycle, which is defined by CS, AS, and DS all being active. The second option is to use an external pull-up on DT to pull DT high within the timing requirements of the microprocessor.
Lucent Technologies Inc.
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TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet February 1999
Timing Characteristics (continued)
MM A[14--0]
READ ADDRESS
t11 CS AS DS R/W t13 D[7--0]
READ DATA
5-7065(F)r.3
t9
t10
t14
Figure 18. Asynchronous Read Cycle Timing Using Only CS
MM A[14--0]
WRITE ADDRESS
t12 CS t9 AS DS R/W D[7--0]
WRITE DATA
t11 t10
5-7066(F)r.3
Figure 19. Asynchronous Write Cycle Timing Using Only CS Table 48. Asynchronous Microprocessor Interface Timing Using Only CS Symbol t9 t10 t11 t12 t13 t14 Description A[14--0], R/W, D[7--0] Input Setup to CS A[14--0], R/W, D[7--0] Input Hold from CS Pulse Width of CS Inactive Pulse Width of CS Active D[7--0] Output Delay from CS (CL = 50 pF) D[7--0] Output Hold from CS (CL = 50 pF) Min 0 0 100 200 -- 0 Max -- -- -- -- 200 -- Unit ns ns ns ns ns ns
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Lucent Technologies Inc.
Preliminary Data Sheet February 1999
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Timing Characteristics (continued)
PCLK t15 CS t15 AS t17 R/W t22 DT t19 t24 D[7--0] t21 A[14--0]
READ ADDRESS
5-7067(F)r.3
t16
t18 t22
t21 t22
HIGH IMPEDANCE t23
t25
Figure 20. Synchronous Read Cycle Timing
PCLK t15 CS t15 AS t17 R/W t22 DT t19 t21 D[7--0] t20 A[14--0]
WRITE ADDRESS
5-7068(F)r.2
t16
t18 t22
t21
t22 HIGH IMPEDANCE t23
WRITE DATA
t21
Figure 21. Synchronous Write Cycle Timing
Lucent Technologies Inc.
59
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet February 1999
Timing Characteristics (continued)
Table 49. Synchronous Microprocessor Interface Timing Symbol t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 Description CS Setup to Rising PCLK Edge CS Hold from Rising PCLK Edge AS Setup to Rising PCLK Edge AS Hold from Rising PCLK Edge R/W, A[14--0] Input Setup to Rising PCLK Edge D[7--0] Input Setup to Rising PCLK Edge R/W, A[14--0], D[7--0] Input Hold from Rising PCLK Edge DT Output Delay from Rising PCLK Edge (CL = 10 pF to 50 pF) DT High Impedance from Falling PCLK Edge (CL = 50 pF) D[7--0] Output Delay from Rising PCLK Edge (CL = 50 pF) D[7--0] Output High Impedance from Rising PCLK Edge (CL = 10 pF to 50 pF) Min 10* 0 6 0 0 0
Max -- -- -- -- -- -- -- 10 7 0
Unit ns ns ns ns ns ns ns ns ns ns ns
0 2.6 -- -- 4
12
* The CS setup timing requirement relative to PCLK can be programmed for either the first or second clock cycle of a microprocessor access using CSV (bit 7) of the general command register. The input setup timing requirement assumes a PCLK frequency of at least 25 MHz. For frequencies slower than 25 MHz, the D[7--0] propagation delay must be less than 40 ns from the rising edge of PCLK which samples AS. When data is driven by the TSI during a synchronous read cycle, good data is driven prior to DT being asserted.
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Lucent Technologies Inc.
Preliminary Data Sheet February 1999
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Timing Characteristics (continued)
TDM highway timing is shown below for the following scenario (i = 0, 1, 2 . . . 31; j = 0, 1, 2 . . . 31):
s s s s
The input CK speed is set to 8.192 MHz. FSYNC is programmed to be active-high and sampled by a rising edge of CK. The RXD[i] highway is set for 0-bit offset and a highway data rate of 4.096 Mbits/s. The TXD[j] highway is set for 0-bit offset and a highway data rate of 8.192 Mbits/s.
FSYNC SAMPLED ACTIVE FSYNC t26 CK (8.192 MHz) t26 RXD[i] (4.096 Mbits/s) TXD[j] (8.192 Mbits/s) TXOE[j]
5-7465(F)r.3
t27
t27
BIT 1 BIT 2 BIT 5 BIT 6 BIT 5
BIT 0
t29
BIT 0 BIT 1 BIT 2 BIT 3
t28
BIT 4 BIT 5 BIT 6 BIT 7
t29
t30
t30
Figure 22. TDM Highway Timing Table 50. TDM Highway Timing Symbol t26 t27 t28 t29 t30 Description FSYNC, RXD[0--31] Setup to Active CK Edge FSYNC, RXD[0--31] Hold from Active CK Edge TXD[0--31] Delay from Active CK Edge (CL = 25 pF) TXD[0--31] High Impedance (CL = 25 pF) TXOE[0--31] Delay from Active CK Edge (CL = 20 pF) Min 10 5 5 -- 5 Max -- -- 15 15 15 Unit ns ns ns ns ns
The TDM highway timing numbers, t26--t30, also apply for all other cases as well, i.e.,
s s s s s s s s
CK speed is 2.048 MHz, 4.096 MHz, or 16.384 MHz. FSYNC is sampled on the falling edge of CK. FSYNC is active-low. RXD[i] is sampled on the falling edge of CK. RXD[i] data rate is 2.048 Mbits/s or 8.192 Mbits/s. TXD[j] is driven on the falling edge of CK. TXD[j] data rate is 2.048 Mbits/s or 4.096 Mbits/s. TXOE[j] is driven on the falling edge of CK. TXOE[j] is driven on the same edge as TXD[j].
Lucent Technologies Inc.
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TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet February 1999
Timing Characteristics (continued)
TCK t31 TMS t32
t31 TDI t33 TDO
t32
t34 HIGH IMPEDANCE
5-7070(F)r.2
Figure 23. JTAG Interface Timing Table 51. JTAG Interface Timing Symbol t31 t32 t33 t34 Description TDI, TMS Setup to Rising TCK Edge TDI, TMS Hold from Rising TCK Edge TDO Delay from Falling TCK Edge (CL = 70 pF) TDO High Impedance from Falling TCK Edge (CL = 70 pF) Min 10 -- 5 -- Max -- 10 35 35 Unit ns ns ns ns
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Lucent Technologies Inc.
Preliminary Data Sheet February 1999
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Outline Diagram
217-Pin PBGA
Dimensions are in millimeters.
23.00 0.20 A1 BALL IDENTIFIER ZONE +0.70 19.50 -0.00
+0.70 19.50 -0.00 23.00 0.20
MOLD COMPOUND PWB
0.36 0.04
1.17 0.05
2.13 0.19 SEATING PLANE 0.20
0.60 0.10
SOLDER BALL
16 SPACES @ 1.27 = 20.32
U T R P N M L K J H G F E D C B A
0.75 0.15
16 SPACES @ 1.27 = 20.32
A1 BALL CORNER
12
34567
8 9 10 11 12 13 14 15 16 17
5-6562(F)
Lucent Technologies Inc.
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TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet February 1999
Ordering Information
Device Code TTSI2K32T3BAL Package 217-pin PBGA Temperature -40 C to +85 C Comcode (Ordering Number) 108269770
DS99-045T1E1 Replaces DS97-475TIC to Incorporate the Following Updates
1. Page 8, Pin D17, added overline to show active-low (TRST). 2. Page 8, removed duplicate E1, E2, E3, E4, E14, E15, E16, and E17 pins. 3. Page 20, Highway Data Rate Selection section, added paragraph on meeting the 8.192 Mbits/s bandwidth requirement for a transmit highway pair at the bottom of the page. 4. Page 22, updated Figure 10, Virtual and Physical Frames on page 22. 5. Page 24, Reset Sequence section, added paragraph on BIST requirement. 6. Page 25--page 28, Low-Latency and Frame-Integrity Modes section updated. 7. Page 29, Test-Pattern Generation section updated. 8. Page 29 and page 30, Test-Pattern Checking section updated. 9. Page 38, Table 15, General Command Register (0x00), removed last sentence in description of bit 2 and bit 1. 10. Page 38, Table 15, General Command Register (0x00), updated bit 0 symbol from GXEN to GXE. 11. Page 39, Table 16, Software Reset Register (0x01), updated bit 0, software reset description. 12. Page 41, Table 22, Interrupt Status Register (0x07), updated bit 4 and bit 2 to reserved status. 13. Page 42, Table 23, Interrupt Mask Register (0x08), updated bit 4 and bit 2 to reserved status. 14. Page 42, Table 23, Interrupt Mask Register (0x08), bit 3 symbol changed from MASKED to MASKERD. 15. Page 44, Table 25, Test-Pattern Style Register (0x0A), updated test-pattern descriptions. 16. Page 45, Table 27, Test-Pattern Checker Upper Time-Slot Register (0x0C), updated description. 17. Page 45, Table 28, Test-Pattern Checker Lower Time-Slot Register (0x0D), updated description. 18. Page 45, Table 30, Test-Pattern Error Injection Register (0x0F), changed register name from test-pattern error selection register to test-pattern error injection register and added sentence to end of description. 19. Page 47, Table 35, Transmit Highway Configuration Register (Byte 0) (0x1000 + 4i), updated bit 3--bit 2 symbol from XCEOFF to XFBOFF. 20. Page 48, Table 37, Transmit Highway Configuration Register (Byte 2) (0x1002 + 4i), updated bit 2 symbol name from XEN to XE. 21. Page 49, Table 38, Receive Highway Configuration Register (Byte 0) (0x1800 + 4i), updated bit 3--bit 2 symbol from RCEOFF to RFBOFF. 22. Page 51, Transmit Highway 3-State Options section and Table 41, Transmit Highway 3-State Options updated. 23. Page 52, Data Store Memory section updated. 24. Page 53, Table 44, Connection Store Memory (Byte 0), changed TSA symbol to RTSA and updated description. 25. Page 53, Table 45, Connection Store Memory (Byte 1), changed PORTNUM symbol to RXHWY. 26. Page 52--page 54, Connection Store Memory section updated. 27. Page 55, Absolute Maximum Ratings table, power dissipation, PD, updated from 450 mW to 440 mW. 28. Page 56, Table 46, Clock Specifications, updated clock period stability for CK. 29. Page 61, Timing Characteristics section, updated Figure 22, TDM Highway Timing and text. 30. Page 61, Table 50, TDM Highway Timing, timing parameter t26, minimum changed from 15 ns to 10 ns.
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Lucent Technologies Inc.
Preliminary Data Sheet February 1999
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Notes
Lucent Technologies Inc.
65
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet February 1999
For additional information, contact your Microelectronics Group Account Manager or the following: http://www.lucent.com/micro INTERNET: docmaster@micro.lucent.com E-MAIL: N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P. R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1189 324 299, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information.
Copyright (c) 1999 Lucent Technologies Inc. All Rights Reserved
February 1999 DS99-045T1E1 (Replaces DS97-475TIC and AY98-029TIC)

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